From: Peter Maydell Date: Wed, 1 Sep 2021 07:33:02 +0000 (+0100) Subject: Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901... X-Git-Tag: v6.2.0-rc0~127 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ec397e90d21269037280633b6058d1f280e27667;p=thirdparty%2Fqemu.git Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging First RISC-V PR for QEMU 6.2 - Add a config for Shakti UART - Fixup virt flash node - Don't override users supplied ISA version - Fixup some CSR accesses - Use g_strjoinv() for virt machine PLIC string config - Fix an overflow in the SiFive CLINT - Add 64-bit register access helpers - Replace tcg_const_* with direct constant usage # gpg: Signature made Wed 01 Sep 2021 03:08:48 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis " [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210901-2: (33 commits) target/riscv: Use {get,dest}_gpr for RVV target/riscv: Tidy trans_rvh.c.inc target/riscv: Use {get,dest}_gpr for RVD target/riscv: Use {get,dest}_gpr for RVF target/riscv: Use gen_shift_imm_fn for slli_uw target/riscv: Use {get,dest}_gpr for RVA target/riscv: Reorg csr instructions target/riscv: Fix hgeie, hgeip target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation target/riscv: Use {get, dest}_gpr for integer load/store target/riscv: Use get_gpr in branches target/riscv: Use extracts for sraiw and srliw target/riscv: Use DisasExtend in shift operations target/riscv: Add DisasExtend to gen_unary target/riscv: Move gen_* helpers for RVB target/riscv: Move gen_* helpers for RVM target/riscv: Use gen_arith for mulh and mulhu target/riscv: Remove gen_arith_div* target/riscv: Add DisasExtend to gen_arith* target/riscv: Introduce DisasExtend and new helpers ... Signed-off-by: Peter Maydell --- ec397e90d21269037280633b6058d1f280e27667