From: Greg Kroah-Hartman Date: Wed, 15 Jan 2025 10:14:29 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v6.1.125~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ec979689c82f067345d85231682a6c6417c9703e;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: risc-v-don-t-enable-all-interrupts-in-trap_init.patch riscv-prefix-irq_-macro-names-with-an-rv_-namespace.patch --- diff --git a/queue-5.4/risc-v-don-t-enable-all-interrupts-in-trap_init.patch b/queue-5.4/risc-v-don-t-enable-all-interrupts-in-trap_init.patch new file mode 100644 index 00000000000..54334629b98 --- /dev/null +++ b/queue-5.4/risc-v-don-t-enable-all-interrupts-in-trap_init.patch @@ -0,0 +1,44 @@ +From 6a1ce99dc4bde564e4a072936f9d41f4a439140e Mon Sep 17 00:00:00 2001 +From: Anup Patel +Date: Sun, 2 Feb 2020 16:32:02 +0530 +Subject: RISC-V: Don't enable all interrupts in trap_init() + +From: Anup Patel + +commit 6a1ce99dc4bde564e4a072936f9d41f4a439140e upstream. + +Historically, we have been enabling all interrupts for each +HART in trap_init(). Ideally, we should only enable M-mode +interrupts for M-mode kernel and S-mode interrupts for S-mode +kernel in trap_init(). + +Currently, we get suprious S-mode interrupts on Kendryte K210 +board running M-mode NO-MMU kernel because we are enabling all +interrupts in trap_init(). To fix this, we only enable software +and external interrupt in trap_init(). In future, trap_init() +will only enable software interrupt and PLIC driver will enable +external interrupt using CPU notifiers. + +Fixes: a4c3733d32a7 ("riscv: abstract out CSR names for supervisor vs machine mode") +Signed-off-by: Anup Patel +Reviewed-by: Atish Patra +Tested-by: Palmer Dabbelt [QMEU virt machine with SMP] +[Palmer: Move the Fixes up to a newer commit] +Reviewed-by: Palmer Dabbelt +Signed-off-by: Palmer Dabbelt +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/kernel/traps.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/riscv/kernel/traps.c ++++ b/arch/riscv/kernel/traps.c +@@ -162,6 +162,6 @@ void __init trap_init(void) + csr_write(CSR_SCRATCH, 0); + /* Set the exception vector address */ + csr_write(CSR_TVEC, &handle_exception); +- /* Enable all interrupts */ +- csr_write(CSR_IE, -1); ++ /* Enable interrupts */ ++ csr_write(CSR_IE, IE_SIE | IE_EIE); + } diff --git a/queue-5.4/riscv-prefix-irq_-macro-names-with-an-rv_-namespace.patch b/queue-5.4/riscv-prefix-irq_-macro-names-with-an-rv_-namespace.patch new file mode 100644 index 00000000000..84b0b11b0e4 --- /dev/null +++ b/queue-5.4/riscv-prefix-irq_-macro-names-with-an-rv_-namespace.patch @@ -0,0 +1,99 @@ +From 2f3035da4019780250658d1ffe486bc324e04805 Mon Sep 17 00:00:00 2001 +From: Paul Walmsley +Date: Fri, 20 Dec 2019 03:09:49 -0800 +Subject: riscv: prefix IRQ_ macro names with an RV_ namespace + +From: Paul Walmsley + +commit 2f3035da4019780250658d1ffe486bc324e04805 upstream. + +"IRQ_TIMER", used in the arch/riscv CSR header file, is a sufficiently +generic macro name that it's used by several source files across the +Linux code base. Some of these other files ultimately include the +arch/riscv CSR include file, causing collisions. Fix by prefixing the +RISC-V csr.h IRQ_ macro names with an RV_ prefix. + +Fixes: a4c3733d32a72 ("riscv: abstract out CSR names for supervisor vs machine mode") +Reported-by: Olof Johansson +Acked-by: Olof Johansson +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/include/asm/csr.h | 18 +++++++++--------- + arch/riscv/kernel/irq.c | 6 +++--- + drivers/irqchip/irq-sifive-plic.c | 2 +- + 3 files changed, 13 insertions(+), 13 deletions(-) + +--- a/arch/riscv/include/asm/csr.h ++++ b/arch/riscv/include/asm/csr.h +@@ -114,9 +114,9 @@ + # define SR_PIE SR_MPIE + # define SR_PP SR_MPP + +-# define IRQ_SOFT IRQ_M_SOFT +-# define IRQ_TIMER IRQ_M_TIMER +-# define IRQ_EXT IRQ_M_EXT ++# define RV_IRQ_SOFT IRQ_M_SOFT ++# define RV_IRQ_TIMER IRQ_M_TIMER ++# define RV_IRQ_EXT IRQ_M_EXT + #else /* CONFIG_RISCV_M_MODE */ + # define CSR_STATUS CSR_SSTATUS + # define CSR_IE CSR_SIE +@@ -131,15 +131,15 @@ + # define SR_PIE SR_SPIE + # define SR_PP SR_SPP + +-# define IRQ_SOFT IRQ_S_SOFT +-# define IRQ_TIMER IRQ_S_TIMER +-# define IRQ_EXT IRQ_S_EXT ++# define RV_IRQ_SOFT IRQ_S_SOFT ++# define RV_IRQ_TIMER IRQ_S_TIMER ++# define RV_IRQ_EXT IRQ_S_EXT + #endif /* CONFIG_RISCV_M_MODE */ + + /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ +-#define IE_SIE (_AC(0x1, UL) << IRQ_SOFT) +-#define IE_TIE (_AC(0x1, UL) << IRQ_TIMER) +-#define IE_EIE (_AC(0x1, UL) << IRQ_EXT) ++#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) ++#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) ++#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) + + #ifndef __ASSEMBLY__ + +--- a/arch/riscv/kernel/irq.c ++++ b/arch/riscv/kernel/irq.c +@@ -23,11 +23,11 @@ asmlinkage __visible void __irq_entry do + + irq_enter(); + switch (regs->cause & ~CAUSE_IRQ_FLAG) { +- case IRQ_TIMER: ++ case RV_IRQ_TIMER: + riscv_timer_interrupt(); + break; + #ifdef CONFIG_SMP +- case IRQ_SOFT: ++ case RV_IRQ_SOFT: + /* + * We only use software interrupts to pass IPIs, so if a non-SMP + * system gets one, then we don't know what to do. +@@ -35,7 +35,7 @@ asmlinkage __visible void __irq_entry do + riscv_software_interrupt(); + break; + #endif +- case IRQ_EXT: ++ case RV_IRQ_EXT: + handle_arch_irq(regs); + break; + default: +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -262,7 +262,7 @@ static int __init plic_init(struct devic + * Skip contexts other than external interrupts for our + * privilege level. + */ +- if (parent.args[0] != IRQ_EXT) ++ if (parent.args[0] != RV_IRQ_EXT) + continue; + + hartid = plic_find_hart_id(parent.np); diff --git a/queue-5.4/series b/queue-5.4/series index c5d55d66318..a22713f969a 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -49,3 +49,5 @@ riscv-remove-unused-handle_exception-symbol.patch risc-v-avoid-dereferening-null-regs-in-die.patch riscv-avoid-enabling-interrupts-in-die.patch riscv-fix-sleeping-in-invalid-context-in-die.patch +riscv-prefix-irq_-macro-names-with-an-rv_-namespace.patch +risc-v-don-t-enable-all-interrupts-in-trap_init.patch