From: Julian Seward <jseward@acm.org>
Date: Fri, 12 May 2006 17:47:21 +0000 (+0000)
Subject: (1) Fix longstanding bug causing erroneous register zeroing for 'btl'.
X-Git-Tag: svn/VALGRIND_3_2_3^2~66
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ecbf1bc78d030f6223d55ab11bf3ba13bae5ef0f;p=thirdparty%2Fvalgrind.git

(1) Fix longstanding bug causing erroneous register zeroing for 'btl'.
(2) Implement 16-bit versions of bt/bts/btr/btc.  (Fixes #125607)


git-svn-id: svn://svn.valgrind.org/vex/trunk@1612
---

diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c
index 9de659dff3..36fe0c6d48 100644
--- a/VEX/priv/guest-amd64/toIR.c
+++ b/VEX/priv/guest-amd64/toIR.c
@@ -6905,7 +6905,11 @@ ULong dis_bt_G_E ( Prefix pfx, Int sz, Long delta, BtOp op )
    /* Move reg operand from stack back to reg */
    if (epartIsReg(modrm)) {
       /* t_esp still points at it. */
-      putIRegE(sz, pfx, modrm, loadLE(szToITy(sz), mkexpr(t_rsp)) );
+      /* only write the reg if actually modifying it; doing otherwise
+         zeroes the top half erroneously when doing btl due to
+         standard zero-extend rule */
+       if (op != BtOpNone)
+         putIRegE(sz, pfx, modrm, loadLE(szToITy(sz), mkexpr(t_rsp)) );
       putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(sz)) );
    }
 
@@ -13354,22 +13358,22 @@ DisResult disInstr_AMD64_WRK (
 
       case 0xA3: /* BT Gv,Ev */
          if (haveF2orF3(pfx)) goto decode_failure;
-         if (sz != 8 && sz != 4) goto decode_failure;
+         if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
          delta = dis_bt_G_E ( pfx, sz, delta, BtOpNone );
          break;
       case 0xB3: /* BTR Gv,Ev */
          if (haveF2orF3(pfx)) goto decode_failure;
-         if (sz != 8 && sz != 4) goto decode_failure;
+         if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
          delta = dis_bt_G_E ( pfx, sz, delta, BtOpReset );
          break;
       case 0xAB: /* BTS Gv,Ev */
          if (haveF2orF3(pfx)) goto decode_failure;
-         if (sz != 8 && sz != 4) goto decode_failure;
+         if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
          delta = dis_bt_G_E ( pfx, sz, delta, BtOpSet );
          break;
       case 0xBB: /* BTC Gv,Ev */
          if (haveF2orF3(pfx)) goto decode_failure;
-         if (sz != 8 && sz != 4) goto decode_failure;
+         if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
          delta = dis_bt_G_E ( pfx, sz, delta, BtOpComp );
          break;