From: Oliver Upton Date: Wed, 5 Mar 2025 20:26:31 +0000 (-0800) Subject: KVM: arm64: Always support SW_INCR PMU event X-Git-Tag: v6.15-rc1~195^2~2^2~3^2~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ed335722b4571c438c008fc96bf86b9d4705a60f;p=thirdparty%2Fkernel%2Flinux.git KVM: arm64: Always support SW_INCR PMU event Support for SW_INCR is unconditional, as KVM traps accesses to PMSWINC_EL0 and emulates the intended event increment. While it is expected that ~all PMUv3 implementations already advertise this event, non-PMUv3 hardware may not. Tested-by: Janne Grunau Reviewed-by: Marc Zyngier Link: https://lore.kernel.org/r/20250305202641.428114-5-oliver.upton@linux.dev Signed-off-by: Oliver Upton --- diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 104672a0c5a21..62349b670cf92 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -856,6 +856,8 @@ static u64 compute_pmceid0(struct arm_pmu *pmu) { u64 val = __compute_pmceid(pmu, 0); + /* always support SW_INCR */ + val |= BIT(ARMV8_PMUV3_PERFCTR_SW_INCR); /* always support CHAIN */ val |= BIT(ARMV8_PMUV3_PERFCTR_CHAIN); return val;