From: Greg Kroah-Hartman Date: Fri, 7 Aug 2015 01:35:06 +0000 (-0700) Subject: remove some MIPS patches from 4.1 queue X-Git-Tag: v4.1.5~24 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ed467f50b1d199da57a19e51fdb9c835b04f2f85;p=thirdparty%2Fkernel%2Fstable-queue.git remove some MIPS patches from 4.1 queue --- diff --git a/queue-4.1/mips-cps-vec-use-macros-for-various-arithmetics-and-memory-operations.patch b/queue-4.1/mips-cps-vec-use-macros-for-various-arithmetics-and-memory-operations.patch deleted file mode 100644 index a3abf584a44..00000000000 --- a/queue-4.1/mips-cps-vec-use-macros-for-various-arithmetics-and-memory-operations.patch +++ /dev/null @@ -1,114 +0,0 @@ -From b677bc03d757c7d749527cccdd2afcf34ebeeb07 Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:13:33 +0100 -Subject: MIPS: cps-vec: Use macros for various arithmetics and memory operations - -From: Markos Chandras - -commit b677bc03d757c7d749527cccdd2afcf34ebeeb07 upstream. - -Replace lw/sw and various arithmetic instructions with macros so the -code can work on 64-bit kernels as well. - -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10591/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/kernel/cps-vec.S | 32 ++++++++++++++++---------------- - 1 file changed, 16 insertions(+), 16 deletions(-) - ---- a/arch/mips/kernel/cps-vec.S -+++ b/arch/mips/kernel/cps-vec.S -@@ -108,9 +108,9 @@ not_nmi: - mul t1, t1, t2 - - li a0, CKSEG0 -- add a1, a0, t1 -+ PTR_ADD a1, a0, t1 - 1: cache Index_Store_Tag_I, 0(a0) -- add a0, a0, t0 -+ PTR_ADD a0, a0, t0 - bne a0, a1, 1b - nop - icache_done: -@@ -135,11 +135,11 @@ icache_done: - mul t1, t1, t2 - - li a0, CKSEG0 -- addu a1, a0, t1 -- subu a1, a1, t0 -+ PTR_ADDU a1, a0, t1 -+ PTR_SUBU a1, a1, t0 - 1: cache Index_Store_Tag_D, 0(a0) - bne a0, a1, 1b -- add a0, a0, t0 -+ PTR_ADD a0, a0, t0 - dcache_done: - - /* Set Kseg0 CCA to that in s0 */ -@@ -152,7 +152,7 @@ dcache_done: - - /* Enter the coherent domain */ - li t0, 0xff -- sw t0, GCR_CL_COHERENCE_OFS(v1) -+ PTR_S t0, GCR_CL_COHERENCE_OFS(v1) - ehb - - /* Jump to kseg0 */ -@@ -178,9 +178,9 @@ dcache_done: - nop - - /* Off we go! */ -- lw t1, VPEBOOTCFG_PC(v0) -- lw gp, VPEBOOTCFG_GP(v0) -- lw sp, VPEBOOTCFG_SP(v0) -+ PTR_L t1, VPEBOOTCFG_PC(v0) -+ PTR_L gp, VPEBOOTCFG_GP(v0) -+ PTR_L sp, VPEBOOTCFG_SP(v0) - jr t1 - nop - END(mips_cps_core_entry) -@@ -299,15 +299,15 @@ LEAF(mips_cps_core_init) - LEAF(mips_cps_boot_vpes) - /* Retrieve CM base address */ - PTR_LA t0, mips_cm_base -- lw t0, 0(t0) -+ PTR_L t0, 0(t0) - - /* Calculate a pointer to this cores struct core_boot_config */ -- lw t0, GCR_CL_ID_OFS(t0) -+ PTR_L t0, GCR_CL_ID_OFS(t0) - li t1, COREBOOTCFG_SIZE - mul t0, t0, t1 - PTR_LA t1, mips_cps_core_bootcfg -- lw t1, 0(t1) -- addu t0, t0, t1 -+ PTR_L t1, 0(t1) -+ PTR_ADDU t0, t0, t1 - - /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ - has_mt ta2, 1f -@@ -334,8 +334,8 @@ LEAF(mips_cps_boot_vpes) - 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */ - li t1, VPEBOOTCFG_SIZE - mul v0, t9, t1 -- lw ta3, COREBOOTCFG_VPECONFIG(t0) -- addu v0, v0, ta3 -+ PTR_L ta3, COREBOOTCFG_VPECONFIG(t0) -+ PTR_ADDU v0, v0, ta3 - - #ifdef CONFIG_MIPS_MT - -@@ -360,7 +360,7 @@ LEAF(mips_cps_boot_vpes) - ehb - - /* Loop through each VPE */ -- lw ta2, COREBOOTCFG_VPEMASK(t0) -+ PTR_L ta2, COREBOOTCFG_VPEMASK(t0) - move t8, ta2 - li ta1, 0 - diff --git a/queue-4.1/mips-kernel-cps-vec-replace-kseg0-with-ckseg0.patch b/queue-4.1/mips-kernel-cps-vec-replace-kseg0-with-ckseg0.patch deleted file mode 100644 index 7d502cddb53..00000000000 --- a/queue-4.1/mips-kernel-cps-vec-replace-kseg0-with-ckseg0.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 717f14255a52ad445d6f0eca7d0f22f59d6ba1f8 Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:13:32 +0100 -Subject: MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0 - -From: Markos Chandras - -commit 717f14255a52ad445d6f0eca7d0f22f59d6ba1f8 upstream. - -In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0 -so 64-bit kernels can be supported. - -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10590/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/kernel/cps-vec.S | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/kernel/cps-vec.S -+++ b/arch/mips/kernel/cps-vec.S -@@ -107,7 +107,7 @@ not_nmi: - mul t1, t1, t0 - mul t1, t1, t2 - -- li a0, KSEG0 -+ li a0, CKSEG0 - add a1, a0, t1 - 1: cache Index_Store_Tag_I, 0(a0) - add a0, a0, t0 -@@ -134,7 +134,7 @@ icache_done: - mul t1, t1, t0 - mul t1, t1, t2 - -- li a0, KSEG0 -+ li a0, CKSEG0 - addu a1, a0, t1 - subu a1, a1, t0 - 1: cache Index_Store_Tag_D, 0(a0) diff --git a/queue-4.1/mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch b/queue-4.1/mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch deleted file mode 100644 index 72aed6573d9..00000000000 --- a/queue-4.1/mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch +++ /dev/null @@ -1,116 +0,0 @@ -From 81a02e34ded906357deac7003fbb0d36b6cc503f Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:13:29 +0100 -Subject: MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA - -From: Markos Chandras - -commit 81a02e34ded906357deac7003fbb0d36b6cc503f upstream. - -The PTR_LA macro will pick the correct "la" or "dla" macro to -load an address to a register. This gets rids of the following -warnings (and others) when building a 64-bit CPS kernel: - -arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address -arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address -arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address -arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address -[...] - -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10587/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/kernel/cps-vec.S | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - ---- a/arch/mips/kernel/cps-vec.S -+++ b/arch/mips/kernel/cps-vec.S -@@ -60,7 +60,7 @@ LEAF(mips_cps_core_entry) - nop - - /* This is an NMI */ -- la k0, nmi_handler -+ PTR_LA k0, nmi_handler - jr k0 - nop - -@@ -156,7 +156,7 @@ dcache_done: - ehb - - /* Jump to kseg0 */ -- la t0, 1f -+ PTR_LA t0, 1f - jr t0 - nop - -@@ -217,7 +217,7 @@ LEAF(excep_intex) - - .org 0x480 - LEAF(excep_ejtag) -- la k0, ejtag_debug_handler -+ PTR_LA k0, ejtag_debug_handler - jr k0 - nop - END(excep_ejtag) -@@ -237,7 +237,7 @@ LEAF(mips_cps_core_init) - - /* ...and for the moment only 1 VPE */ - dvpe -- la t1, 1f -+ PTR_LA t1, 1f - jr.hb t1 - nop - -@@ -298,14 +298,14 @@ LEAF(mips_cps_core_init) - - LEAF(mips_cps_boot_vpes) - /* Retrieve CM base address */ -- la t0, mips_cm_base -+ PTR_LA t0, mips_cm_base - lw t0, 0(t0) - - /* Calculate a pointer to this cores struct core_boot_config */ - lw t0, GCR_CL_ID_OFS(t0) - li t1, COREBOOTCFG_SIZE - mul t0, t0, t1 -- la t1, mips_cps_core_bootcfg -+ PTR_LA t1, mips_cps_core_bootcfg - lw t1, 0(t1) - addu t0, t0, t1 - -@@ -351,7 +351,7 @@ LEAF(mips_cps_boot_vpes) - - 1: /* Enter VPE configuration state */ - dvpe -- la t1, 1f -+ PTR_LA t1, 1f - jr.hb t1 - nop - 1: mfc0 t1, CP0_MVPCONTROL -@@ -445,7 +445,7 @@ LEAF(mips_cps_boot_vpes) - /* This VPE should be offline, halt the TC */ - li t0, TCHALT_H - mtc0 t0, CP0_TCHALT -- la t0, 1f -+ PTR_LA t0, 1f - 1: jr.hb t0 - nop - -@@ -466,10 +466,10 @@ LEAF(mips_cps_boot_vpes) - .set noat - lw $1, TI_CPU(gp) - sll $1, $1, LONGLOG -- la \dest, __per_cpu_offset -+ PTR_LA \dest, __per_cpu_offset - addu $1, $1, \dest - lw $1, 0($1) -- la \dest, cps_cpu_state -+ PTR_LA \dest, cps_cpu_state - addu \dest, \dest, $1 - .set pop - .endm diff --git a/queue-4.1/mips-kernel-cps-vec-replace-mips32r2-isa-level-with-mips64r2.patch b/queue-4.1/mips-kernel-cps-vec-replace-mips32r2-isa-level-with-mips64r2.patch deleted file mode 100644 index 76286421a58..00000000000 --- a/queue-4.1/mips-kernel-cps-vec-replace-mips32r2-isa-level-with-mips64r2.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 977e043d5ea1270ce985e4c165724ff91dc3c3e2 Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:13:30 +0100 -Subject: MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2 - -From: Markos Chandras - -commit 977e043d5ea1270ce985e4c165724ff91dc3c3e2 upstream. - -mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2 -in preparation for 64-bit CPS support. - -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10588/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/kernel/cps-vec.S | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/kernel/cps-vec.S -+++ b/arch/mips/kernel/cps-vec.S -@@ -229,7 +229,7 @@ LEAF(mips_cps_core_init) - nop - - .set push -- .set mips32r2 -+ .set mips64r2 - .set mt - - /* Only allow 1 TC per VPE to execute... */ -@@ -346,7 +346,7 @@ LEAF(mips_cps_boot_vpes) - nop - - .set push -- .set mips32r2 -+ .set mips64r2 - .set mt - - 1: /* Enter VPE configuration state */ diff --git a/queue-4.1/mips-kernel-cps-vec-use-ta0-ta3-pseudo-registers-for-64-bit.patch b/queue-4.1/mips-kernel-cps-vec-use-ta0-ta3-pseudo-registers-for-64-bit.patch deleted file mode 100644 index f6f178018d4..00000000000 --- a/queue-4.1/mips-kernel-cps-vec-use-ta0-ta3-pseudo-registers-for-64-bit.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 0586ac75cd0746a4d5c43372dabcea8739ae0176 Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:13:31 +0100 -Subject: MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit - -From: Markos Chandras - -commit 0586ac75cd0746a4d5c43372dabcea8739ae0176 upstream. - -The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This -breaks the build on 64-bit. As a result of which, use the pseudo-registers -ta0-ta3 to make the code compatible with 64-bit. - -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10589/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/kernel/cps-vec.S | 42 +++++++++++++++++++++--------------------- - 1 file changed, 21 insertions(+), 21 deletions(-) - ---- a/arch/mips/kernel/cps-vec.S -+++ b/arch/mips/kernel/cps-vec.S -@@ -250,25 +250,25 @@ LEAF(mips_cps_core_init) - mfc0 t0, CP0_MVPCONF0 - srl t0, t0, MVPCONF0_PVPE_SHIFT - andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT) -- addiu t7, t0, 1 -+ addiu ta3, t0, 1 - - /* If there's only 1, we're done */ - beqz t0, 2f - nop - - /* Loop through each VPE within this core */ -- li t5, 1 -+ li ta1, 1 - - 1: /* Operate on the appropriate TC */ -- mtc0 t5, CP0_VPECONTROL -+ mtc0 ta1, CP0_VPECONTROL - ehb - - /* Bind TC to VPE (1:1 TC:VPE mapping) */ -- mttc0 t5, CP0_TCBIND -+ mttc0 ta1, CP0_TCBIND - - /* Set exclusive TC, non-active, master */ - li t0, VPECONF0_MVP -- sll t1, t5, VPECONF0_XTC_SHIFT -+ sll t1, ta1, VPECONF0_XTC_SHIFT - or t0, t0, t1 - mttc0 t0, CP0_VPECONF0 - -@@ -280,8 +280,8 @@ LEAF(mips_cps_core_init) - mttc0 t0, CP0_TCHALT - - /* Next VPE */ -- addiu t5, t5, 1 -- slt t0, t5, t7 -+ addiu ta1, ta1, 1 -+ slt t0, ta1, ta3 - bnez t0, 1b - nop - -@@ -310,7 +310,7 @@ LEAF(mips_cps_boot_vpes) - addu t0, t0, t1 - - /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ -- has_mt t6, 1f -+ has_mt ta2, 1f - li t9, 0 - - /* Find the number of VPEs present in the core */ -@@ -334,13 +334,13 @@ LEAF(mips_cps_boot_vpes) - 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */ - li t1, VPEBOOTCFG_SIZE - mul v0, t9, t1 -- lw t7, COREBOOTCFG_VPECONFIG(t0) -- addu v0, v0, t7 -+ lw ta3, COREBOOTCFG_VPECONFIG(t0) -+ addu v0, v0, ta3 - - #ifdef CONFIG_MIPS_MT - - /* If the core doesn't support MT then return */ -- bnez t6, 1f -+ bnez ta2, 1f - nop - jr ra - nop -@@ -360,12 +360,12 @@ LEAF(mips_cps_boot_vpes) - ehb - - /* Loop through each VPE */ -- lw t6, COREBOOTCFG_VPEMASK(t0) -- move t8, t6 -- li t5, 0 -+ lw ta2, COREBOOTCFG_VPEMASK(t0) -+ move t8, ta2 -+ li ta1, 0 - - /* Check whether the VPE should be running. If not, skip it */ --1: andi t0, t6, 1 -+1: andi t0, ta2, 1 - beqz t0, 2f - nop - -@@ -373,7 +373,7 @@ LEAF(mips_cps_boot_vpes) - mfc0 t0, CP0_VPECONTROL - ori t0, t0, VPECONTROL_TARGTC - xori t0, t0, VPECONTROL_TARGTC -- or t0, t0, t5 -+ or t0, t0, ta1 - mtc0 t0, CP0_VPECONTROL - ehb - -@@ -384,8 +384,8 @@ LEAF(mips_cps_boot_vpes) - - /* Calculate a pointer to the VPEs struct vpe_boot_config */ - li t0, VPEBOOTCFG_SIZE -- mul t0, t0, t5 -- addu t0, t0, t7 -+ mul t0, t0, ta1 -+ addu t0, t0, ta3 - - /* Set the TC restart PC */ - lw t1, VPEBOOTCFG_PC(t0) -@@ -423,9 +423,9 @@ LEAF(mips_cps_boot_vpes) - mttc0 t0, CP0_VPECONF0 - - /* Next VPE */ --2: srl t6, t6, 1 -- addiu t5, t5, 1 -- bnez t6, 1b -+2: srl ta2, ta2, 1 -+ addiu ta1, ta1, 1 -+ bnez ta2, 1b - nop - - /* Leave VPE configuration state */ diff --git a/queue-4.1/mips-kernel-smp-cps-fix-64-bit-compatibility-errors-due-to-pointer-casting.patch b/queue-4.1/mips-kernel-smp-cps-fix-64-bit-compatibility-errors-due-to-pointer-casting.patch deleted file mode 100644 index 2d3628b5927..00000000000 --- a/queue-4.1/mips-kernel-smp-cps-fix-64-bit-compatibility-errors-due-to-pointer-casting.patch +++ /dev/null @@ -1,69 +0,0 @@ -From fd5ed3066bb2f47814fe53cdc56d11a678551ae1 Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:13:28 +0100 -Subject: MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer casting - -From: Markos Chandras - -commit fd5ed3066bb2f47814fe53cdc56d11a678551ae1 upstream. - -Commit 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") added hotplug -support in the SMP/CPS implementation but it introduced a few build problems -on 64-bit kernels due to pointer being casted to and from 'int' C types. We -fix this problem by using 'unsigned long' instead which should match the size -of the pointers in 32/64-bit kernels. Finally, we fix the comment since the -CM base address is loaded to v1($3) instead of v0. - -Fixes the following build problems: - -arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt': -arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of -different size [-Werror=pointer-to-int-cast] -[...] -arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die': -arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer -from integer of different size [-Werror=int-to-pointer-cast] - -cc1: all warnings being treated as errors - -Fixes: 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10586/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/kernel/smp-cps.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/mips/kernel/smp-cps.c -+++ b/arch/mips/kernel/smp-cps.c -@@ -133,7 +133,7 @@ static void __init cps_prepare_cpus(unsi - /* - * Patch the start of mips_cps_core_entry to provide: - * -- * v0 = CM base address -+ * v1 = CM base address - * s0 = kseg0 CCA - */ - entry_code = (u32 *)&mips_cps_core_entry; -@@ -369,7 +369,7 @@ void play_dead(void) - - static void wait_for_sibling_halt(void *ptr_cpu) - { -- unsigned cpu = (unsigned)ptr_cpu; -+ unsigned cpu = (unsigned long)ptr_cpu; - unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); - unsigned halted; - unsigned long flags; -@@ -430,7 +430,7 @@ static void cps_cpu_die(unsigned int cpu - */ - err = smp_call_function_single(cpu_death_sibling, - wait_for_sibling_halt, -- (void *)cpu, 1); -+ (void *)(unsigned long)cpu, 1); - if (err) - panic("Failed to call remote sibling CPU\n"); - } diff --git a/queue-4.1/revert-mips-kconfig-disable-smp-cps-for-64-bit.patch b/queue-4.1/revert-mips-kconfig-disable-smp-cps-for-64-bit.patch deleted file mode 100644 index e537cfd6b04..00000000000 --- a/queue-4.1/revert-mips-kconfig-disable-smp-cps-for-64-bit.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 1c885357da2d3cf62132e611c0beaf4cdf607dd9 Mon Sep 17 00:00:00 2001 -From: Markos Chandras -Date: Wed, 1 Jul 2015 09:31:14 +0100 -Subject: Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit" - -From: Markos Chandras - -commit 1c885357da2d3cf62132e611c0beaf4cdf607dd9 upstream. - -This reverts commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e. - -SMP/CPS is now supported on 64bit cores. - -Reviewed-by: Paul Burton -Signed-off-by: Markos Chandras -Cc: linux-mips@linux-mips.org -Patchwork: https://patchwork.linux-mips.org/patch/10592/ -Signed-off-by: Ralf Baechle -Signed-off-by: Greg Kroah-Hartman - ---- - arch/mips/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2220,7 +2220,7 @@ config MIPS_CMP - - config MIPS_CPS - bool "MIPS Coherent Processing System support" -- depends on SYS_SUPPORTS_MIPS_CPS && !64BIT -+ depends on SYS_SUPPORTS_MIPS_CPS - select MIPS_CM - select MIPS_CPC - select MIPS_CPS_PM if HOTPLUG_CPU diff --git a/queue-4.1/series b/queue-4.1/series index de71439a1f0..f1d5c650e2b 100644 --- a/queue-4.1/series +++ b/queue-4.1/series @@ -9,15 +9,8 @@ arm-dts-dra7x-evm-prevent-glitch-on-dcan1-pinmux.patch arm-dts-am57xx-beagle-x15-provide-supply-for-usb2_phy2.patch arm-8404-1-dma-mapping-fix-off-by-one-error-in-bitmap-size-check.patch arm-imx6-gpc-always-enable-pu-domain-if-config_pm-is-not-set.patch -revert-mips-kconfig-disable-smp-cps-for-64-bit.patch mips-fix-erroneous-jr-emulation-for-mips-r6.patch mips-c-r4k-fix-cache-flushing-for-mt-cores.patch -mips-kernel-smp-cps-fix-64-bit-compatibility-errors-due-to-pointer-casting.patch -mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch -mips-kernel-cps-vec-replace-mips32r2-isa-level-with-mips64r2.patch -mips-kernel-cps-vec-use-ta0-ta3-pseudo-registers-for-64-bit.patch -mips-kernel-cps-vec-replace-kseg0-with-ckseg0.patch -mips-cps-vec-use-macros-for-various-arithmetics-and-memory-operations.patch mips-require-o32-fp64-support-for-mips64-with-o32-compat.patch mips-fpu.h-allow-64-bit-fpu-on-a-64-bit-mips-r6-cpu.patch can-replace-timestamp-as-unique-skb-attribute.patch