From: Jagan Teki Date: Tue, 13 Nov 2018 11:16:08 +0000 (+0530) Subject: clk: sunxi-ng: a64: Fix gate bit of DSI DPHY X-Git-Tag: v5.0-rc1~171^2~6^3~1^2~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ee678706e46d0d185c27cc214ad97828e0643159;p=thirdparty%2Fkernel%2Flinux.git clk: sunxi-ng: a64: Fix gate bit of DSI DPHY DSI DPHY gate bit on MIPI DSI clock register is bit 15 not bit 30. Signed-off-by: Jagan Teki Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 884d8f7863c41..1f45b20ad752b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -586,7 +586,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; static const u8 dsi_dphy_table[] = { 0, 2, }; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, dsi_dphy_table, - 0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT); + 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);