From: Lad Prabhakar Date: Mon, 7 Apr 2025 16:51:58 +0000 (+0100) Subject: clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation X-Git-Tag: v6.16-rc1~114^2~2^2~1^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ef224dd26ca3554ba810996710bcf671bc1c6be9;p=thirdparty%2Flinux.git clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation Update the clock enable/disable logic to follow the latest hardware manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to confirm the clock state. According to the manual, enabling a clock requires setting the CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON bit. Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and confirming the clock has stopped via the CPG_CLK_MON bit. Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then validate CLK_ON for a more accurate clock status evaluation. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index d5ad752b05825..bcc496e8cbcda 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -573,11 +573,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) if (clock->mon_index >= 0) { offset = GET_CLK_MON_OFFSET(clock->mon_index); bitmask = BIT(clock->mon_bit); - } else { - offset = GET_CLK_ON_OFFSET(clock->on_index); - bitmask = BIT(clock->on_bit); + + if (!(readl(priv->base + offset) & bitmask)) + return 0; } + offset = GET_CLK_ON_OFFSET(clock->on_index); + bitmask = BIT(clock->on_bit); + return readl(priv->base + offset) & bitmask; }