From: Koby Elbaz Date: Thu, 5 Oct 2023 15:06:18 +0000 (-0400) Subject: drm/xe: map MMIO BAR according to the num of tiles in device desc X-Git-Tag: v6.8-rc1~111^2~7^2~296 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ef29b390c734;p=thirdparty%2Flinux.git drm/xe: map MMIO BAR according to the num of tiles in device desc When MMIO BAR is initially mapped, the driver assumes a single tile device. However, former memory allocations take all tiles into account. First, a common standard for resource usage is needed here. Second, with the next (6th) patch in this series, the MMIO BAR remapping will be done only if a reduced-tile device is attached. Signed-off-by: Koby Elbaz Reviewed-by: Ofir Bitton Reviewed-by: Moti Haimovski Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c index 054ad752303f6..52e4572e3c4ac 100644 --- a/drivers/gpu/drm/xe/xe_mmio.c +++ b/drivers/gpu/drm/xe/xe_mmio.c @@ -383,14 +383,13 @@ int xe_mmio_init(struct xe_device *xe) int err; /* - * Map the first 16MB of th BAR, which includes the registers (0-4MB), - * reserved space (4MB-8MB), and GGTT (8MB-16MB) for a single tile. - * This will get remapped later if we determine that we're running - * on a multi-tile system. + * Map the maximum expected BAR size, which will get remapped later + * if we determine that we're running on a reduced-tile system. + * The first 16MB of the BAR, belong to the root tile, and include: + * registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB). */ - xe->mmio.size = SZ_16M; - xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar, - xe->mmio.size); + xe->mmio.size = (SZ_16M + xe->info.tile_mmio_ext_size) * xe->info.tile_count; + xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar, xe->mmio.size); if (xe->mmio.regs == NULL) { drm_err(&xe->drm, "failed to map registers\n"); return -EIO;