From: Ville Syrjälä Date: Tue, 1 Apr 2025 16:37:49 +0000 (+0300) Subject: drm/i915: Apply the combo PLL frac w/a on DG1 X-Git-Tag: v6.16-rc1~144^2~20^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=efaa1177c31be89483dfd3919348b3535f602b5e;p=thirdparty%2Flinux.git drm/i915: Apply the combo PLL frac w/a on DG1 DG1 apparently needs the combo PLL fractional divider w/a with 38.4 MHz refclk as well. This isn't listed in bspec, but looking at the hsd it looks like it was possibly just missed due to no one having a DG1 around at the time. This gives us slightly more accurate clocks on DG1. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250401163752.6412-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak --- diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index ec7feef1ef59b..76ab55ee4b80a 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2604,6 +2604,7 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display) { return ((display->platform.elkhartlake && IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) || + display->platform.dg1 || display->platform.tigerlake || display->platform.alderlake_s || display->platform.alderlake_p) &&