From: WANG Xuerui <git@xen0n.name>
Date: Sun, 23 Mar 2025 09:30:38 +0000 (+0800)
Subject: LoongArch: Support LA32R aliases rdcnt{vl,vh,id}.w
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=eff93f19cb973c58fbc9899e4e111d583e4a1dbe;p=thirdparty%2Fbinutils-gdb.git

LoongArch: Support LA32R aliases rdcnt{vl,vh,id}.w

These LA32R instructions are in fact special cases of the LA32S/LA64
rdtime{l,h}.w (with only one output operand instead of two, the other
one being forced to $zero), but are named differently in the LA32R
ISA manual nevertheless.

As the LA32R names are more memorable to a degree (especially for those
having difficulties remembering which operand corresponds to the node
ID), support them by making them aliases of the corresponding LA32S/LA64
instruction respectively, and make them render as such in disassembly.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---

diff --git a/gas/testsuite/gas/loongarch/fix_op.d b/gas/testsuite/gas/loongarch/fix_op.d
index 7125f2e3309..05e7403d15c 100644
--- a/gas/testsuite/gas/loongarch/fix_op.d
+++ b/gas/testsuite/gas/loongarch/fix_op.d
@@ -132,3 +132,6 @@ Disassembly of section .text:
 [ 	]+1e8:[ 	]+00df04a4 [ 	]+bstrpick.d[ 	]+[ 	]+\$a0, \$a1, 0x1f, 0x1
 [ 	]+1ec:[ 	]+00e000a4 [ 	]+bstrpick.d[ 	]+[ 	]+\$a0, \$a1, 0x20, 0x0
 [ 	]+1f0:[ 	]+00ff00a4 [ 	]+bstrpick.d[ 	]+[ 	]+\$a0, \$a1, 0x3f, 0x0
+[ 	]+1f4:[ 	]+00006004 [ 	]+rdcntvl.w[ 	]+[ 	]+\$a0
+[ 	]+1f8:[ 	]+000060a0 [ 	]+rdcntid.w[ 	]+[ 	]+\$a1
+[ 	]+1fc:[ 	]+00006404 [ 	]+rdcntvh.w[ 	]+[ 	]+\$a0
diff --git a/gas/testsuite/gas/loongarch/fix_op.s b/gas/testsuite/gas/loongarch/fix_op.s
index d0523f959fb..876913bfdfb 100644
--- a/gas/testsuite/gas/loongarch/fix_op.s
+++ b/gas/testsuite/gas/loongarch/fix_op.s
@@ -123,3 +123,8 @@ bstrpick.d  $r4,$r5,0,0
 bstrpick.d  $r4,$r5,31,1
 bstrpick.d  $r4,$r5,32,0
 bstrpick.d  $r4,$r5,63,0
+
+# LA32R aliases
+rdcntvl.w  $r4
+rdcntid.w  $r5
+rdcntvh.w  $r4
diff --git a/gas/testsuite/gas/loongarch/insn_alias_32.d b/gas/testsuite/gas/loongarch/insn_alias_32.d
index 753eae7a8f9..3aa716f5b8f 100644
--- a/gas/testsuite/gas/loongarch/insn_alias_32.d
+++ b/gas/testsuite/gas/loongarch/insn_alias_32.d
@@ -17,3 +17,6 @@ Disassembly of section .text:
   18:	60000080 	blt         	\$a0, \$zero, 0	# 18 <L1\+0x18>
   1c:	64000080 	bge         	\$a0, \$zero, 0	# 1c <L1\+0x1c>
   20:	64000004 	bge         	\$zero, \$a0, 0	# 20 <L1\+0x20>
+  24:	00006004 	rdtimel.w   	\$a0, \$zero
+  28:	000060a0 	rdtimel.w   	\$zero, \$a1
+  2c:	00006406 	rdtimeh.w   	\$a2, \$zero
diff --git a/gas/testsuite/gas/loongarch/insn_alias_32.s b/gas/testsuite/gas/loongarch/insn_alias_32.s
index 8027e32a5a6..492e52a0c40 100644
--- a/gas/testsuite/gas/loongarch/insn_alias_32.s
+++ b/gas/testsuite/gas/loongarch/insn_alias_32.s
@@ -8,3 +8,8 @@ L1:
   bltz  $a0,.L1
   bgez  $a0,.L1
   blez  $a0,.L1
+
+  # LA32R aliases
+  rdcntvl.w $a0
+  rdcntid.w $a1
+  rdcntvh.w $a2
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index a172a2afadc..fa53021cfae 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -454,6 +454,9 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
 static struct loongarch_opcode loongarch_alias_opcodes[] =
 {
   /* match,	mask,		name,		format,				macro,	include, exclude, pinfo.  */
+  { 0x00006000, 0xffffffe0,	"rdcntvl.w",	"r0:5",				0,	0, 0, INSN_DIS_ALIAS }, /* rdtimel.w rd, zero */
+  { 0x00006000, 0xfffffc1f,	"rdcntid.w",	"r5:5",				0,	0, 0, INSN_DIS_ALIAS }, /* rdtimel.w zero, rj */
+  { 0x00006400, 0xffffffe0,	"rdcntvh.w",	"r0:5",				0,	0, 0, INSN_DIS_ALIAS }, /* rdtimeh.w rd, zero */
   { 0x00150000,	0xfffffc00,	"move",		"r0:5,r5:5",			0,	0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */
   { 0x02800000, 0xffc003e0,	"li.w",		"r0:5,s10:12",			0,	0, 0, INSN_DIS_ALIAS }, /* addi.w rd, zero, simm */
   { 0x02c00000, 0xffc003e0,	"li.d",		"r0:5,s10:12",			0,	0, 0, INSN_DIS_ALIAS }, /* addi.d rd, zero, simm */
@@ -494,7 +497,10 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
   { 0x00005400, 0xfffffc00,	"bitrev.d",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00005800, 0xfffffc00,	"ext.w.h",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00005c00, 0xfffffc00,	"ext.w.b",	"r0:5,r5:5",			0,			0,	0,	0 },
+  { 0x0,	0x0,		"rdcntvl.w",	"r",				"rdtimel.w %1,$r0",	0,	0,	0 },
+  { 0x0,	0x0,		"rdcntid.w",	"r",				"rdtimel.w $r0,%1",	0,	0,	0 },
   { 0x00006000, 0xfffffc00,	"rdtimel.w",	"r0:5,r5:5",			0,			0,	0,	0 },
+  { 0x0,	0x0,		"rdcntvh.w",	"r",				"rdtimeh.w %1,$r0",	0,	0,	0 },
   { 0x00006400, 0xfffffc00,	"rdtimeh.w",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00006800, 0xfffffc00,	"rdtime.d",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00006c00, 0xfffffc00,	"cpucfg",	"r0:5,r5:5",			0,			0,	0,	0 },