From: Matthieu Longo Date: Thu, 16 May 2024 11:36:14 +0000 (+0100) Subject: aarch64: add SPMU feature and its associated registers X-Git-Tag: gdb-15-branchpoint~82 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f01ae0392ed9e7012ae33fdcf972ee4508fb7db2;p=thirdparty%2Fbinutils-gdb.git aarch64: add SPMU feature and its associated registers --- diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l index 05431cc501b..9cf94755cf6 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs-bad.l @@ -204,6 +204,20 @@ .*: Error: selected processor does not support system register name 'pmicfiltr_el0' .*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmzr_el0' +.*: Error: selected processor does not support system register name 'spmaccessr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmaccessr_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmcr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmcr_el0' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmdevaff_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmintenset_el1' +.*: Info: macro invoked from here +.*: Error: selected processor does not support system register name 'spmintenset_el1' +.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmecr_el1' .*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'pmecr_el1' diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d index 9913c2be6d3..e420f7077a6 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.d @@ -128,6 +128,13 @@ Disassembly of section \.text: .*: d51b9600 msr pmicfiltr_el0, x0 .*: d53b9600 mrs x0, pmicfiltr_el0 .*: d51b9d80 msr pmzr_el0, x0 +.*: d5109d60 msr spmaccessr_el1, x0 +.*: d5309d60 mrs x0, spmaccessr_el1 +.*: d5139c00 msr spmcr_el0, x0 +.*: d5339c00 mrs x0, spmcr_el0 +.*: d5309dc0 mrs x0, spmdevaff_el1 +.*: d5109e20 msr spmintenset_el1, x0 +.*: d5309e20 mrs x0, spmintenset_el1 .*: d5189ea0 msr pmecr_el1, x0 .*: d5389ea0 mrs x0, pmecr_el1 .*: d5189ee0 msr pmiar_el1, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s index 318d8bb9097..6a01cb43289 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s +++ b/gas/testsuite/gas/aarch64/sysreg/armv8_9-a-sysregs.s @@ -107,6 +107,12 @@ rw_sys_reg sys_reg=pmicfiltr_el0 xreg=x0 r=1 w=1 msr pmzr_el0, x0 + /* FEAT_SPMU */ + rw_sys_reg sys_reg=spmaccessr_el1 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=spmcr_el0 xreg=x0 r=1 w=1 + rw_sys_reg sys_reg=spmdevaff_el1 xreg=x0 r=1 w=0 + rw_sys_reg sys_reg=spmintenset_el1 xreg=x0 r=1 w=1 + /* FEAT_SEBEP Extension. */ rw_sys_reg sys_reg=pmecr_el1 xreg=x0 r=1 w=1 rw_sys_reg sys_reg=pmiar_el1 xreg=x0 r=1 w=1 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index e8fe93ef127..1ec0b66a654 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -218,6 +218,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PMUv3_SS, /* Performance Monitors Instruction Counter Extension. */ AARCH64_FEATURE_PMUv3_ICNTR, + /* System Performance Monitors Extension */ + AARCH64_FEATURE_SPMU, /* Performance Monitors Synchronous-Exception-Based Event Extension. */ AARCH64_FEATURE_SEBEP, /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */ @@ -309,6 +311,7 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, PMUv3p9) \ | AARCH64_FEATBIT (X, PMUv3_SS) \ | AARCH64_FEATBIT (X, PMUv3_ICNTR) \ + | AARCH64_FEATBIT (X, SPMU) \ | AARCH64_FEATBIT (X, SEBEP) \ | AARCH64_FEATBIT (X, PREDRES2) \ ) diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 8b65673a5d6..7cbc9a4811f 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -867,6 +867,10 @@ SYSREG ("sp_el0", CPENC (3,0,4,1,0), 0, AARCH64_NO_FEATURES) SYSREG ("sp_el1", CPENC (3,4,4,1,0), 0, AARCH64_NO_FEATURES) SYSREG ("sp_el2", CPENC (3,6,4,1,0), 0, AARCH64_NO_FEATURES) + SYSREG ("spmaccessr_el1", CPENC (2,0,9,13,3), F_ARCHEXT, AARCH64_FEATURE (SPMU)) + SYSREG ("spmcr_el0", CPENC (2,3,9,12,0), F_ARCHEXT, AARCH64_FEATURE (SPMU)) + SYSREG ("spmdevaff_el1", CPENC (2,0,9,13,6), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (SPMU)) + SYSREG ("spmintenset_el1", CPENC (2,0,9,14,1), F_ARCHEXT, AARCH64_FEATURE (SPMU)) SYSREG ("spsel", CPENC (3,0,4,2,0), 0, AARCH64_NO_FEATURES) SYSREG ("spsr_abt", CPENC (3,4,4,3,1), 0, AARCH64_NO_FEATURES) SYSREG ("spsr_el1", CPENC (3,0,4,0,0), 0, AARCH64_NO_FEATURES)