From: Stefan Hajnoczi Date: Tue, 20 May 2025 14:26:30 +0000 (-0400) Subject: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f0737158b483e7ec2b2512145aeab888b85cc1f7;p=thirdparty%2Fqemu.git Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * target/riscv: clean up supported MMU modes, declarative CPU definitions, remove .instance_post_init (reviewed by Alistair) * qom: reverse order of instance_post_init calls * qapi/misc-target: doc and standard improvements for SGX * hw/pci-host/gt64120: Fix endianness handling * i386/hvf: Make CPUID_HT supported * i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmgsLEsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroMosgf+IbsERBx/JTsjv2tKfCdAKXGmZ6xv # JIb6SzXkuA0TBScUm0U1zluimNWHqqnSWQ/ogxhw69rqEkAZiFGbahpt9udD19kN # 7oSLmj64a0a4uJZmWeMQ3rPO8zehg6t5K0sKXyR3d49pghw9NCzWabXdDypaV4VC # sgl9zS46PMjG12XBSq7zwQsUPGwIE6OICtxM/UMgvlqdoI+sZjYU39MpmBf5I0DQ # /VwGnZPc1pVwZqYn5sV075N4bjN+JYlaZN4+OcuRrU5bw4M8ZEwKxL+/b65ilp5S # EqDXuxAilMS/0orC7YpCEf9Dryy/w8n3q4ejV8LQ5K6gnsOFTTurdNlWog== # =bsKR # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 May 2025 03:16:27 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini " [full] # gpg: aka "Paolo Bonzini " [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits) qom: reverse order of instance_post_init calls target/riscv: remove .instance_post_init target/riscv: convert Xiangshan Nanhu to RISCVCPUDef target/riscv: convert Ventana V1 to RISCVCPUDef target/riscv: convert TT Ascalon to RISCVCPUDef target/riscv: convert THead C906 to RISCVCPUDef target/riscv: generalize custom CSR functionality target/riscv: th: make CSR insertion test a bit more intuitive target/riscv: convert SiFive U models to RISCVCPUDef target/riscv: convert ibex CPU models to RISCVCPUDef target/riscv: convert SiFive E CPU models to RISCVCPUDef target/riscv: convert dynamic CPU models to RISCVCPUDef target/riscv: convert bare CPU models to RISCVCPUDef target/riscv: convert profile CPU models to RISCVCPUDef target/riscv: convert abstract CPU classes to RISCVCPUDef target/riscv: add more RISCVCPUDef fields target/riscv: include default value in cpu_cfg_fields.h.inc target/riscv: move RISCVCPUConfig fields to a header file target/riscv: merge riscv_cpu_class_init with the class_base function target/riscv: store RISCVCPUDef struct directly in the class ... Signed-off-by: Stefan Hajnoczi --- f0737158b483e7ec2b2512145aeab888b85cc1f7