From: Phil Reid Date: Fri, 28 Jun 2019 03:19:09 +0000 (+0800) Subject: dt-bindings: clock: cdce925: Add regulator documentation X-Git-Tag: v5.4-rc1~97^2~1^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f121edb69799f52f9166c2458286f3738b360147;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: clock: cdce925: Add regulator documentation The cdce925 has two separate supply pins. Document the bindings for them. Signed-off-by: Phil Reid Link: https://lkml.kernel.org/r/1561691950-42154-2-git-send-email-preid@electromag.com.au Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt index 0d01f2d5cc36e..26544c85202af 100644 --- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt +++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt @@ -24,6 +24,8 @@ Required properties: Optional properties: - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a board, or to compensate for external influences. +- vdd-supply: A regulator node for Vdd +- vddout-supply: A regulator node for Vddout For all PLL1, PLL2, ... an optional child node can be used to specify spread spectrum clocking parameters for a board. @@ -41,6 +43,8 @@ Example: clocks = <&xtal_27Mhz>; #clock-cells = <1>; xtal-load-pf = <5>; + vdd-supply = <&1v8-reg>; + vddout-supply = <&3v3-reg>; /* PLL options to get SSC 1% centered */ PLL2 { spread-spectrum = <4>;