From: Greg Kroah-Hartman Date: Thu, 9 May 2013 17:23:42 +0000 (-0700) Subject: 3.8-stable patches X-Git-Tag: v3.9.2~45 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f15516134393c9bc69b33f91c2797e38b9bcf91a;p=thirdparty%2Fkernel%2Fstable-queue.git 3.8-stable patches added patches: drm-i915-set-cpt-fdi-rx-polarity-bits-based-on-vbt.patch drm-i915-use-mlc-l3-for-context-objects.patch drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch --- diff --git a/queue-3.8/drm-i915-set-cpt-fdi-rx-polarity-bits-based-on-vbt.patch b/queue-3.8/drm-i915-set-cpt-fdi-rx-polarity-bits-based-on-vbt.patch new file mode 100644 index 00000000000..7d093c75f4d --- /dev/null +++ b/queue-3.8/drm-i915-set-cpt-fdi-rx-polarity-bits-based-on-vbt.patch @@ -0,0 +1,108 @@ +From 3f704fa2778d3fe45e6529825a5c7a8bcbc686f4 Mon Sep 17 00:00:00 2001 +From: Paulo Zanoni +Date: Mon, 8 Apr 2013 15:48:07 -0300 +Subject: drm/i915: set CPT FDI RX polarity bits based on VBT + +From: Paulo Zanoni + +commit 3f704fa2778d3fe45e6529825a5c7a8bcbc686f4 upstream. + +Check the VBT to see if the machine has inverted FDI RX polarity on +CPT. Based on this bit, set the appropriate bit on the TRANS_CHICKEN2 +registers. + +This should fix some machines that were showing black screens on all +outputs. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60029 +Signed-off-by: Paulo Zanoni +Reviewed-by: Imre Deak +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_drv.h | 1 + + drivers/gpu/drm/i915/i915_reg.h | 2 +- + drivers/gpu/drm/i915/intel_bios.c | 6 ++++-- + drivers/gpu/drm/i915/intel_bios.h | 4 +++- + drivers/gpu/drm/i915/intel_pm.c | 9 +++++++-- + 5 files changed, 16 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_drv.h ++++ b/drivers/gpu/drm/i915/i915_drv.h +@@ -711,6 +711,7 @@ typedef struct drm_i915_private { + unsigned int int_crt_support:1; + unsigned int lvds_use_ssc:1; + unsigned int display_clock_mode:1; ++ unsigned int fdi_rx_polarity_inverted:1; + int lvds_ssc_freq; + unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ + unsigned int lvds_val; /* used for checking LVDS channel mode */ +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -3839,7 +3839,7 @@ + #define _TRANSB_CHICKEN2 0xf1064 + #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) + #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) +- ++#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) + + #define SOUTH_CHICKEN1 0xc2000 + #define FDIA_PHASE_SYNC_SHIFT_OVR 19 +--- a/drivers/gpu/drm/i915/intel_bios.c ++++ b/drivers/gpu/drm/i915/intel_bios.c +@@ -351,12 +351,14 @@ parse_general_features(struct drm_i915_p + dev_priv->lvds_ssc_freq = + intel_bios_ssc_frequency(dev, general->ssc_freq); + dev_priv->display_clock_mode = general->display_clock_mode; +- DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n", ++ dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; ++ DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", + dev_priv->int_tv_support, + dev_priv->int_crt_support, + dev_priv->lvds_use_ssc, + dev_priv->lvds_ssc_freq, +- dev_priv->display_clock_mode); ++ dev_priv->display_clock_mode, ++ dev_priv->fdi_rx_polarity_inverted); + } + } + +--- a/drivers/gpu/drm/i915/intel_bios.h ++++ b/drivers/gpu/drm/i915/intel_bios.h +@@ -127,7 +127,9 @@ struct bdb_general_features { + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; +- u8 rsvd9:6; /* finish byte */ ++ u8 rsvd9:1; ++ u8 fdi_rx_polarity_inverted:1; ++ u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -3560,6 +3560,7 @@ static void cpt_init_clock_gating(struct + { + struct drm_i915_private *dev_priv = dev->dev_private; + int pipe; ++ uint32_t val; + + /* + * On Ibex Peak and Cougar Point, we need to disable clock +@@ -3572,8 +3573,12 @@ static void cpt_init_clock_gating(struct + /* The below fixes the weird display corruption, a few pixels shifted + * downward, on (only) LVDS of some HP laptops with IVY. + */ +- for_each_pipe(pipe) +- I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); ++ for_each_pipe(pipe) { ++ val = TRANS_CHICKEN2_TIMING_OVERRIDE; ++ if (dev_priv->fdi_rx_polarity_inverted) ++ val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; ++ I915_WRITE(TRANS_CHICKEN2(pipe), val); ++ } + /* WADP0ClockGatingDisable */ + for_each_pipe(pipe) { + I915_WRITE(TRANS_CHICKEN1(pipe), diff --git a/queue-3.8/drm-i915-use-mlc-l3-for-context-objects.patch b/queue-3.8/drm-i915-use-mlc-l3-for-context-objects.patch new file mode 100644 index 00000000000..6521c352eb9 --- /dev/null +++ b/queue-3.8/drm-i915-use-mlc-l3-for-context-objects.patch @@ -0,0 +1,50 @@ +From 4615d4c9e27eda42c3e965f208a4b4065841498c Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Mon, 8 Apr 2013 14:28:40 +0100 +Subject: drm/i915: Use MLC (l3$) for context objects + +From: Chris Wilson + +commit 4615d4c9e27eda42c3e965f208a4b4065841498c upstream. + +Enabling context support increases SwapBuffers latency by about 20% +(measured on an i7-3720qm). We can offset that loss slightly by enabling +faster caching for the contexts. As they are not backed by any +particular cache (such as the sampler or render caches) our only option +is to select the generic mid-level cache. This reduces the latency of +the swap by about 5%. + +Oddly this effect can be observed running smokin-guns on IVB at +1280x1024: +Using BLT copies for swaps: 151.67 fps +Using Render copies for swaps (unpatched): 141.70 fps +With contexts disabled: 150.23 fps +With contexts in L3$: 150.77 fps + +Signed-off-by: Chris Wilson +Cc: Ben Widawsky +Cc: Kenneth Graunke +Reviewed-by: Kenneth Graunke +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_gem_context.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/gpu/drm/i915/i915_gem_context.c ++++ b/drivers/gpu/drm/i915/i915_gem_context.c +@@ -157,6 +157,13 @@ create_hw_context(struct drm_device *dev + return ERR_PTR(-ENOMEM); + } + ++ if (INTEL_INFO(dev)->gen >= 7) { ++ ret = i915_gem_object_set_cache_level(ctx->obj, ++ I915_CACHE_LLC_MLC); ++ if (ret) ++ goto err_out; ++ } ++ + /* The ring associated with the context object is handled by the normal + * object tracking code. We give an initial ring value simple to pass an + * assertion in the context switch code. diff --git a/queue-3.8/drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch b/queue-3.8/drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch new file mode 100644 index 00000000000..2ee41169371 --- /dev/null +++ b/queue-3.8/drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch @@ -0,0 +1,76 @@ +From 25ff1195f8a0b3724541ae7bbe331b4296de9c06 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Thu, 4 Apr 2013 21:31:03 +0100 +Subject: drm/i915: Workaround incoherence between fences and LLC across multiple CPUs + +From: Chris Wilson + +commit 25ff1195f8a0b3724541ae7bbe331b4296de9c06 upstream. + +In order to fully serialize access to the fenced region and the update +to the fence register we need to take extreme measures on SNB+, and +manually flush writes to memory prior to writing the fence register in +conjunction with the memory barriers placed around the register write. + +Fixes i-g-t/gem_fence_thrash + +v2: Bring a bigger gun +v3: Switch the bigger gun for heavier bullets (Arjan van de Ven) +v4: Remove changes for working generations. +v5: Reduce to a per-cpu wbinvd() call prior to updating the fences. +v6: Rewrite comments to ellide forgotten history. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62191 +Signed-off-by: Chris Wilson +Cc: Jon Bloomfield +Tested-by: Jon Bloomfield (v2) +Reviewed-by: Jesse Barnes +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_gem.c | 26 ++++++++++++++++++++++---- + 1 file changed, 22 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_gem.c ++++ b/drivers/gpu/drm/i915/i915_gem.c +@@ -2662,17 +2662,35 @@ static inline int fence_number(struct dr + return fence - dev_priv->fence_regs; + } + ++static void i915_gem_write_fence__ipi(void *data) ++{ ++ wbinvd(); ++} ++ + static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, + struct drm_i915_fence_reg *fence, + bool enable) + { +- struct drm_i915_private *dev_priv = obj->base.dev->dev_private; +- int reg = fence_number(dev_priv, fence); ++ struct drm_device *dev = obj->base.dev; ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ int fence_reg = fence_number(dev_priv, fence); + +- i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); ++ /* In order to fully serialize access to the fenced region and ++ * the update to the fence register we need to take extreme ++ * measures on SNB+. In theory, the write to the fence register ++ * flushes all memory transactions before, and coupled with the ++ * mb() placed around the register write we serialise all memory ++ * operations with respect to the changes in the tiler. Yet, on ++ * SNB+ we need to take a step further and emit an explicit wbinvd() ++ * on each processor in order to manually flush all memory ++ * transactions before updating the fence register. ++ */ ++ if (HAS_LLC(obj->base.dev)) ++ on_each_cpu(i915_gem_write_fence__ipi, NULL, 1); ++ i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL); + + if (enable) { +- obj->fence_reg = reg; ++ obj->fence_reg = fence_reg; + fence->obj = obj; + list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); + } else { diff --git a/queue-3.8/series b/queue-3.8/series index f16fb50d5f3..b5eca5ba27a 100644 --- a/queue-3.8/series +++ b/queue-3.8/series @@ -37,3 +37,6 @@ drm-i915-fix-detection-of-base-of-stolen-memory.patch drm-i915-fix-sdvo-connector-get_hw_state-function.patch drm-i915-add-no-lvds-quirk-for-fujitsu-esprimo-q900.patch drm-i915-fix-sdvo-connector-and-encoder-get_hw_state-functions.patch +drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch +drm-i915-use-mlc-l3-for-context-objects.patch +drm-i915-set-cpt-fdi-rx-polarity-bits-based-on-vbt.patch