From: Greg Kroah-Hartman Date: Thu, 26 Jul 2018 14:50:01 +0000 (+0200) Subject: 4.17-stable patches X-Git-Tag: v3.18.117~18 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f1b5fd78a0aeaaa583e18c9aa0c12041b190c218;p=thirdparty%2Fkernel%2Fstable-queue.git 4.17-stable patches added patches: clk-aspeed-mark-bclk-pcie-and-dclk-vga-as-critical.patch clk-aspeed-support-hpll-strapping-on-ast2400.patch clk-mvebu-armada-37xx-periph-fix-switching-cpu-rate-from-300mhz-to-1.2ghz.patch mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch mips-fix-off-by-one-in-pci_resource_to_user.patch --- diff --git a/queue-4.17/clk-aspeed-mark-bclk-pcie-and-dclk-vga-as-critical.patch b/queue-4.17/clk-aspeed-mark-bclk-pcie-and-dclk-vga-as-critical.patch new file mode 100644 index 00000000000..d53f8e70181 --- /dev/null +++ b/queue-4.17/clk-aspeed-mark-bclk-pcie-and-dclk-vga-as-critical.patch @@ -0,0 +1,38 @@ +From 974c7c6d7ba5a4b12d99456b0599aa6326dc2b69 Mon Sep 17 00:00:00 2001 +From: Joel Stanley +Date: Thu, 7 Jun 2018 16:39:59 +0930 +Subject: clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical + +From: Joel Stanley + +commit 974c7c6d7ba5a4b12d99456b0599aa6326dc2b69 upstream. + +This is used by the host to talk to the BMC's PCIe slave device. The BMC +is not involved, but the clock needs to be enabled so the host can use +the device. + +Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") +Cc: stable@vger.kernel.org # 4.15 +Acked-by: Andrew Jeffery +Tested-by: Lei YU +Signed-off-by: Joel Stanley +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/clk-aspeed.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/clk-aspeed.c ++++ b/drivers/clk/clk-aspeed.c +@@ -88,8 +88,8 @@ static const struct aspeed_gate_data asp + [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ + [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ + [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ +- [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ +- [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ ++ [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */ ++ [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ + [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, + [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ + [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ diff --git a/queue-4.17/clk-aspeed-support-hpll-strapping-on-ast2400.patch b/queue-4.17/clk-aspeed-support-hpll-strapping-on-ast2400.patch new file mode 100644 index 00000000000..9fd8f387cc9 --- /dev/null +++ b/queue-4.17/clk-aspeed-support-hpll-strapping-on-ast2400.patch @@ -0,0 +1,101 @@ +From 565b9937f44d5ab7956339b6c105c03471ce3243 Mon Sep 17 00:00:00 2001 +From: Joel Stanley +Date: Fri, 29 Jun 2018 08:45:40 +0930 +Subject: clk: aspeed: Support HPLL strapping on ast2400 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Joel Stanley + +commit 565b9937f44d5ab7956339b6c105c03471ce3243 upstream. + +The HPLL can be configured through a register (SCU24), however some +platforms chose to configure it through the strapping settings and do +not use the register. This was not noticed as the logic for bit 18 in +SCU24 was confused: set means programmed, but the driver read it as set +means strapped. + +This gives us the correct HPLL value on Palmetto systems, from which +most of the peripheral clocks are generated. + +Fixes: 5eda5d79e4be ("clk: Add clock driver for ASPEED BMC SoCs") +Cc: stable@vger.kernel.org # v4.15 +Reviewed-by: Cédric Le Goater +Signed-off-by: Joel Stanley +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/clk-aspeed.c | 42 +++++++++++++++++++++++++++++------------- + 1 file changed, 29 insertions(+), 13 deletions(-) + +--- a/drivers/clk/clk-aspeed.c ++++ b/drivers/clk/clk-aspeed.c +@@ -22,7 +22,7 @@ + #define ASPEED_MPLL_PARAM 0x20 + #define ASPEED_HPLL_PARAM 0x24 + #define AST2500_HPLL_BYPASS_EN BIT(20) +-#define AST2400_HPLL_STRAPPED BIT(18) ++#define AST2400_HPLL_PROGRAMMED BIT(18) + #define AST2400_HPLL_BYPASS_EN BIT(17) + #define ASPEED_MISC_CTRL 0x2c + #define UART_DIV13_EN BIT(12) +@@ -530,29 +530,45 @@ builtin_platform_driver(aspeed_clk_drive + static void __init aspeed_ast2400_cc(struct regmap *map) + { + struct clk_hw *hw; +- u32 val, freq, div; ++ u32 val, div, clkin, hpll; ++ const u16 hpll_rates[][4] = { ++ {384, 360, 336, 408}, ++ {400, 375, 350, 425}, ++ }; ++ int rate; + + /* + * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by + * strapping + */ + regmap_read(map, ASPEED_STRAP, &val); +- if (val & CLKIN_25MHZ_EN) +- freq = 25000000; +- else if (val & AST2400_CLK_SOURCE_SEL) +- freq = 48000000; +- else +- freq = 24000000; +- hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); +- pr_debug("clkin @%u MHz\n", freq / 1000000); ++ rate = (val >> 8) & 3; ++ if (val & CLKIN_25MHZ_EN) { ++ clkin = 25000000; ++ hpll = hpll_rates[1][rate]; ++ } else if (val & AST2400_CLK_SOURCE_SEL) { ++ clkin = 48000000; ++ hpll = hpll_rates[0][rate]; ++ } else { ++ clkin = 24000000; ++ hpll = hpll_rates[0][rate]; ++ } ++ hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin); ++ pr_debug("clkin @%u MHz\n", clkin / 1000000); + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, +- * and we assume that it is enabled ++ * and we assume that it is enabled. It can be configured through the ++ * HPLL_PARAM register, or set to a specified frequency by strapping. + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); +- WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured"); +- aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val); ++ if (val & AST2400_HPLL_PROGRAMMED) ++ hw = aspeed_ast2400_calc_pll("hpll", val); ++ else ++ hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0, ++ hpll * 1000000); ++ ++ aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw; + + /* + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) diff --git a/queue-4.17/clk-mvebu-armada-37xx-periph-fix-switching-cpu-rate-from-300mhz-to-1.2ghz.patch b/queue-4.17/clk-mvebu-armada-37xx-periph-fix-switching-cpu-rate-from-300mhz-to-1.2ghz.patch new file mode 100644 index 00000000000..a3034b7ed34 --- /dev/null +++ b/queue-4.17/clk-mvebu-armada-37xx-periph-fix-switching-cpu-rate-from-300mhz-to-1.2ghz.patch @@ -0,0 +1,97 @@ +From 61c40f35f5cd6f67ccbd7319a1722eb78c815989 Mon Sep 17 00:00:00 2001 +From: Gregory CLEMENT +Date: Tue, 19 Jun 2018 14:34:45 +0200 +Subject: clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz + +From: Gregory CLEMENT + +commit 61c40f35f5cd6f67ccbd7319a1722eb78c815989 upstream. + +Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz +respectively) to L0 frequency (1.2 Ghz) requires a significant amount +of time to let VDD stabilize to the appropriate voltage. This amount of +time is large enough that it cannot be covered by the hardware +countdown register. Due to this, the CPU might start operating at L0 +before the voltage is stabilized, leading to CPU stalls. + +To work around this problem, we prevent switching directly from the +L2/L3 frequencies to the L0 frequency, and instead switch to the L1 +frequency in-between. The sequence therefore becomes: + +1. First switch from L2/L3(200/300MHz) to L1(600MHZ) +2. Sleep 20ms for stabling VDD voltage +3. Then switch from L1(600MHZ) to L0(1200Mhz). + +It is based on the work done by Ken Ma + +Cc: stable@vger.kernel.org +Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") +Signed-off-by: Gregory CLEMENT +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/mvebu/armada-37xx-periph.c | 38 +++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/drivers/clk/mvebu/armada-37xx-periph.c ++++ b/drivers/clk/mvebu/armada-37xx-periph.c +@@ -35,6 +35,7 @@ + #define CLK_SEL 0x10 + #define CLK_DIS 0x14 + ++#define ARMADA_37XX_DVFS_LOAD_1 1 + #define LOAD_LEVEL_NR 4 + + #define ARMADA_37XX_NB_L0L1 0x18 +@@ -507,6 +508,40 @@ static long clk_pm_cpu_round_rate(struct + return -EINVAL; + } + ++/* ++ * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz ++ * respectively) to L0 frequency (1.2 Ghz) requires a significant ++ * amount of time to let VDD stabilize to the appropriate ++ * voltage. This amount of time is large enough that it cannot be ++ * covered by the hardware countdown register. Due to this, the CPU ++ * might start operating at L0 before the voltage is stabilized, ++ * leading to CPU stalls. ++ * ++ * To work around this problem, we prevent switching directly from the ++ * L2/L3 frequencies to the L0 frequency, and instead switch to the L1 ++ * frequency in-between. The sequence therefore becomes: ++ * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ) ++ * 2. Sleep 20ms for stabling VDD voltage ++ * 3. Then switch from L1(600MHZ) to L0(1200Mhz). ++ */ ++static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base) ++{ ++ unsigned int cur_level; ++ ++ if (rate != 1200 * 1000 * 1000) ++ return; ++ ++ regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level); ++ cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK; ++ if (cur_level <= ARMADA_37XX_DVFS_LOAD_1) ++ return; ++ ++ regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD, ++ ARMADA_37XX_NB_CPU_LOAD_MASK, ++ ARMADA_37XX_DVFS_LOAD_1); ++ msleep(20); ++} ++ + static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +@@ -537,6 +572,9 @@ static int clk_pm_cpu_set_rate(struct cl + */ + reg = ARMADA_37XX_NB_CPU_LOAD; + mask = ARMADA_37XX_NB_CPU_LOAD_MASK; ++ ++ clk_pm_cpu_set_rate_wa(rate, base); ++ + regmap_update_bits(base, reg, mask, load_level); + + return rate; diff --git a/queue-4.17/mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch b/queue-4.17/mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch new file mode 100644 index 00000000000..60284a970ba --- /dev/null +++ b/queue-4.17/mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch @@ -0,0 +1,39 @@ +From bc88ad2efd11f29e00a4fd60fcd1887abfe76833 Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Fri, 20 Jul 2018 13:58:21 +0200 +Subject: MIPS: ath79: fix register address in ath79_ddr_wb_flush() + +From: Felix Fietkau + +commit bc88ad2efd11f29e00a4fd60fcd1887abfe76833 upstream. + +ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets +need to be a multiple of 4 in order to access the intended register. + +Signed-off-by: Felix Fietkau +Signed-off-by: John Crispin +Signed-off-by: Paul Burton +Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") +Patchwork: https://patchwork.linux-mips.org/patch/19912/ +Cc: Alban Bedel +Cc: James Hogan +Cc: Ralf Baechle +Cc: linux-mips@linux-mips.org +Cc: stable@vger.kernel.org # 4.2+ +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/ath79/common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); + + void ath79_ddr_wb_flush(u32 reg) + { +- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg; ++ void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); + + /* Flush the DDR write buffer. */ + __raw_writel(0x1, flush_reg); diff --git a/queue-4.17/mips-fix-off-by-one-in-pci_resource_to_user.patch b/queue-4.17/mips-fix-off-by-one-in-pci_resource_to_user.patch new file mode 100644 index 00000000000..c0e4503bfbc --- /dev/null +++ b/queue-4.17/mips-fix-off-by-one-in-pci_resource_to_user.patch @@ -0,0 +1,47 @@ +From 38c0a74fe06da3be133cae3fb7bde6a9438e698b Mon Sep 17 00:00:00 2001 +From: Paul Burton +Date: Thu, 12 Jul 2018 09:33:04 -0700 +Subject: MIPS: Fix off-by-one in pci_resource_to_user() + +From: Paul Burton + +commit 38c0a74fe06da3be133cae3fb7bde6a9438e698b upstream. + +The MIPS implementation of pci_resource_to_user() introduced in v3.12 by +commit 4c2924b725fb ("MIPS: PCI: Use pci_resource_to_user to map pci +memory space properly") incorrectly sets *end to the address of the +byte after the resource, rather than the last byte of the resource. + +This results in userland seeing resources as a byte larger than they +actually are, for example a 32 byte BAR will be reported by a tool such +as lspci as being 33 bytes in size: + + Region 2: I/O ports at 1000 [disabled] [size=33] + +Correct this by subtracting one from the calculated end address, +reporting the correct address to userland. + +Signed-off-by: Paul Burton +Reported-by: Rui Wang +Fixes: 4c2924b725fb ("MIPS: PCI: Use pci_resource_to_user to map pci memory space properly") +Cc: James Hogan +Cc: Ralf Baechle +Cc: Wolfgang Grandegger +Cc: linux-mips@linux-mips.org +Cc: stable@vger.kernel.org # v3.12+ +Patchwork: https://patchwork.linux-mips.org/patch/19829/ +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/pci/pci.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -54,5 +54,5 @@ void pci_resource_to_user(const struct p + phys_addr_t size = resource_size(rsrc); + + *start = fixup_bigphys_addr(rsrc->start, size); +- *end = rsrc->start + size; ++ *end = rsrc->start + size - 1; + } diff --git a/queue-4.17/series b/queue-4.17/series index 997f9122c60..dccb3e76a2d 100644 --- a/queue-4.17/series +++ b/queue-4.17/series @@ -1,2 +1,7 @@ kvm-vmx-support-msr_ia32_arch_capabilities-as-a-feature-msr.patch revert-iommu-intel-iommu-enable-config_dma_direct_ops-y-and-clean-up-intel_-alloc-free-_coherent.patch +mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch +mips-fix-off-by-one-in-pci_resource_to_user.patch +clk-mvebu-armada-37xx-periph-fix-switching-cpu-rate-from-300mhz-to-1.2ghz.patch +clk-aspeed-mark-bclk-pcie-and-dclk-vga-as-critical.patch +clk-aspeed-support-hpll-strapping-on-ast2400.patch