From: Andrew Cagney <cagney@redhat.com>
Date: Fri, 14 Nov 1997 08:27:38 +0000 (+0000)
Subject:        * mips.igen: Tag vr5000 instructions.
X-Git-Tag: gdb-4_18~4271
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f23e93dab0704098167aa45ef45243cc8df2fa42;p=thirdparty%2Fbinutils-gdb.git

   * mips.igen: Tag vr5000 instructions.
        (ANDI): Was missing mipsIV model, fix assembler syntax.
        (do_c_cond_fmt): New function.
        (C.cond.fmt): Handle mips I-III which do not support CC field
        separatly.
        (bc1): Handle mips IV which do not have a delaed FCC separatly.
        (SDR): Mask paddr when BigEndianMem, not the converse as specified
        in IV3.2 spec.
        (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
        vr5000 which saves LO in a GPR separatly.
        * configure.in (enable-sim-igen): For vr5000, select vr5000
        specific instructions.
        * configure: Re-generate.
---

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 8f685b812f1..bde6b56034f 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,34 @@
+Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* mips.igen: Tag vr5000 instructions.
+	(ANDI): Was missing mipsIV model, fix assembler syntax.
+	(do_c_cond_fmt): New function.
+	(C.cond.fmt): Handle mips I-III which do not support CC field
+ 	separatly.
+	(bc1): Handle mips IV which do not have a delaed FCC separatly.
+	(SDR): Mask paddr when BigEndianMem, not the converse as specified
+ 	in IV3.2 spec.
+	(DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
+ 	vr5000 which saves LO in a GPR separatly.
+	
+	* configure.in (enable-sim-igen): For vr5000, select vr5000
+ 	specific instructions.
+	* configure: Re-generate.
+	
+Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* Makefile.in (SIM_OBJS): Add sim-fpu module.
+
+	* interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
+ 	fmt_uninterpreted_64 bit cases to switch.  Convert to
+ 	fmt_formatted,
+
+	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
+
+	* mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
+ 	as specified in IV3.2 spec.
+	(MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
+
 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* mips.igen: Delay slot branches add OFFSET to NIA not CIA.
diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index 2df6fcc5e58..1949aeda67e 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -121,8 +121,12 @@ case "${target}" in
   mips64vr54*-*-*)	sim_default_gen=IGEN
 			sim_use_gen=IGEN
 			sim_igen_machine="vr5400"
+			#sim_igen_machine="vr5000,vr5400 -G gen-muli-sim"
 			;;
 # end-sanitize-vr5400
+  mips64vr5*-*-*)	sim_default_gen=IGEN
+			sim_igen_machine="vr5000"
+			;;
   mips16*-*-*)		sim_default_gen=M16
 			;;
   mips32*-*-*)		sim_default_gen=IGEN