From: Atish Patra Date: Fri, 10 Jan 2025 08:21:33 +0000 (-0800) Subject: target/riscv: Add properties for counter delegation ISA extensions X-Git-Tag: v10.0.0-rc0~83^2~18 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f2548886b3dff228b82e91808553616c4b8d14a8;p=thirdparty%2Fqemu.git target/riscv: Add properties for counter delegation ISA extensions This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-5-e83d797ae294@rivosinc.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f5772ae5b..da40f68715 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), @@ -199,6 +200,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 4fe2144ec7..561f5119b6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,6 +78,8 @@ struct RISCVCPUConfig { bool ext_ztso; bool ext_smstateen; bool ext_sstc; + bool ext_smcdeleg; + bool ext_ssccfg; bool ext_smcntrpmf; bool ext_smcsrind; bool ext_sscsrind;