From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Thu, 20 Jun 2024 15:01:21 +0000 (+0800)
Subject: clk: qcom: gcc-ipq6018: update sdcc max clock frequency
X-Git-Tag: v6.11-rc1~109^2^2~2^2~1
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f2743ae3ff84579981ac513f512b9df945d109c0;p=thirdparty%2Flinux.git

clk: qcom: gcc-ipq6018: update sdcc max clock frequency

The mmc controller of the IPQ6018 does not support HS400 mode.
So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 9e58851013663..2e411d874662c 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 	F(96000000, P_GPLL2, 12, 0, 0),
 	F(177777778, P_GPLL0, 4.5, 0, 0),
 	F(192000000, P_GPLL2, 6, 0, 0),
-	F(384000000, P_GPLL2, 3, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
 	{ }
 };