From: Greg Kroah-Hartman Date: Thu, 13 Aug 2015 21:12:48 +0000 (-0700) Subject: 3.10-stable patches X-Git-Tag: v3.10.87~36 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f41768627a74031cbb4e3c981c74ef8d3c672a3d;p=thirdparty%2Fkernel%2Fstable-queue.git 3.10-stable patches added patches: ipmi-fix-timeout-calculation-when-bmc-is-disconnected.patch mfd-sm501-dbg_regs-attribute-must-be-read-only.patch perf-x86-amd-rework-amd-pmu-init-code.patch --- diff --git a/queue-3.10/ipmi-fix-timeout-calculation-when-bmc-is-disconnected.patch b/queue-3.10/ipmi-fix-timeout-calculation-when-bmc-is-disconnected.patch new file mode 100644 index 00000000000..4f086f74602 --- /dev/null +++ b/queue-3.10/ipmi-fix-timeout-calculation-when-bmc-is-disconnected.patch @@ -0,0 +1,47 @@ +From e21404dc0ac7ac971c1e36274b48bb460463f4e5 Mon Sep 17 00:00:00 2001 +From: Xie XiuQi +Date: Fri, 24 Jan 2014 14:00:52 -0600 +Subject: ipmi: fix timeout calculation when bmc is disconnected + +From: Xie XiuQi + +commit e21404dc0ac7ac971c1e36274b48bb460463f4e5 upstream. + +Loading ipmi_si module while bmc is disconnected, we found the timeout +is longer than 5 secs. Actually it takes about 3 mins and 20 +secs.(HZ=250) + +error message as below: + Dec 12 19:08:59 linux kernel: IPMI BT: timeout in RD_WAIT [ ] 1 retries left + Dec 12 19:08:59 linux kernel: BT: write 4 bytes seq=0x01 03 18 00 01 + [...] + Dec 12 19:12:19 linux kernel: IPMI BT: timeout in RD_WAIT [ ] + Dec 12 19:12:19 linux kernel: failed 2 retries, sending error response + Dec 12 19:12:19 linux kernel: IPMI: BT reset (takes 5 secs) + Dec 12 19:12:19 linux kernel: IPMI BT: flag reset [ ] + +Function wait_for_msg_done() use schedule_timeout_uninterruptible(1) to +sleep 1 tick, so we should subtract jiffies_to_usecs(1) instead of 100 +usecs from timeout. + +Reported-by: Hu Shiyuan +Signed-off-by: Xie XiuQi +Signed-off-by: Corey Minyard +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/char/ipmi/ipmi_si_intf.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/char/ipmi/ipmi_si_intf.c ++++ b/drivers/char/ipmi/ipmi_si_intf.c +@@ -2717,7 +2717,7 @@ static int wait_for_msg_done(struct smi_ + smi_result == SI_SM_CALL_WITH_TICK_DELAY) { + schedule_timeout_uninterruptible(1); + smi_result = smi_info->handlers->event( +- smi_info->si_sm, 100); ++ smi_info->si_sm, jiffies_to_usecs(1)); + } else if (smi_result == SI_SM_CALL_WITHOUT_DELAY) { + smi_result = smi_info->handlers->event( + smi_info->si_sm, 0); diff --git a/queue-3.10/mfd-sm501-dbg_regs-attribute-must-be-read-only.patch b/queue-3.10/mfd-sm501-dbg_regs-attribute-must-be-read-only.patch new file mode 100644 index 00000000000..828ecc753b8 --- /dev/null +++ b/queue-3.10/mfd-sm501-dbg_regs-attribute-must-be-read-only.patch @@ -0,0 +1,38 @@ +From 8a8320c2e78d1b619a8fa8eb5ae946b8691de604 Mon Sep 17 00:00:00 2001 +From: Guenter Roeck +Date: Sun, 8 Sep 2013 00:25:36 -0700 +Subject: mfd: sm501: dbg_regs attribute must be read-only + +From: Guenter Roeck + +commit 8a8320c2e78d1b619a8fa8eb5ae946b8691de604 upstream. + +Fix: + +sm501 sm501: SM501 At b3e00000: Version 050100a0, 8 Mb, IRQ 100 +Attribute dbg_regs: write permission without 'store' +------------[ cut here ]------------ +WARNING: at drivers/base/core.c:620 + +dbg_regs does not have a write function and must therefore be marked +as read-only. + +Signed-off-by: Guenter Roeck +Signed-off-by: Lee Jones +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mfd/sm501.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mfd/sm501.c ++++ b/drivers/mfd/sm501.c +@@ -1232,7 +1232,7 @@ static ssize_t sm501_dbg_regs(struct dev + } + + +-static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL); ++static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL); + + /* sm501_init_reg + * diff --git a/queue-3.10/perf-x86-amd-rework-amd-pmu-init-code.patch b/queue-3.10/perf-x86-amd-rework-amd-pmu-init-code.patch new file mode 100644 index 00000000000..a60ce5dc58c --- /dev/null +++ b/queue-3.10/perf-x86-amd-rework-amd-pmu-init-code.patch @@ -0,0 +1,97 @@ +From 1b45adcd9a503428e6de6b39bc6892d86c9c1d41 Mon Sep 17 00:00:00 2001 +From: Peter Zijlstra +Date: Tue, 21 May 2013 13:05:37 +0200 +Subject: perf/x86/amd: Rework AMD PMU init code + +From: Peter Zijlstra + +commit 1b45adcd9a503428e6de6b39bc6892d86c9c1d41 upstream. + +Josh reported that his QEMU is a bad hardware emulator and trips a +WARN in the AMD PMU init code. He requested the WARN be turned into a +pr_err() or similar. + +While there, rework the code a little. + +Reported-by: Josh Boyer +Acked-by: Robert Richter +Acked-by: Jacob Shin +Cc: Stephane Eranian +Signed-off-by: Peter Zijlstra +Link: http://lkml.kernel.org/r/20130521110537.GG26912@twins.programming.kicks-ass.net +Signed-off-by: Ingo Molnar +Cc: Guenter Roeck +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/cpu/perf_event_amd.c | 34 +++++++++++++++++----------------- + 1 file changed, 17 insertions(+), 17 deletions(-) + +--- a/arch/x86/kernel/cpu/perf_event_amd.c ++++ b/arch/x86/kernel/cpu/perf_event_amd.c +@@ -648,48 +648,48 @@ static __initconst const struct x86_pmu + .cpu_dead = amd_pmu_cpu_dead, + }; + +-static int setup_event_constraints(void) ++static int __init amd_core_pmu_init(void) + { +- if (boot_cpu_data.x86 == 0x15) ++ if (!cpu_has_perfctr_core) ++ return 0; ++ ++ switch (boot_cpu_data.x86) { ++ case 0x15: ++ pr_cont("Fam15h "); + x86_pmu.get_event_constraints = amd_get_event_constraints_f15h; +- return 0; +-} ++ break; + +-static int setup_perfctr_core(void) +-{ +- if (!cpu_has_perfctr_core) { +- WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h, +- KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!"); ++ default: ++ pr_err("core perfctr but no constraints; unknown hardware!\n"); + return -ENODEV; + } + +- WARN(x86_pmu.get_event_constraints == amd_get_event_constraints, +- KERN_ERR "hw perf events core counters need constraints handler!"); +- + /* + * If core performance counter extensions exists, we must use + * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also +- * x86_pmu_addr_offset(). ++ * amd_pmu_addr_offset(). + */ + x86_pmu.eventsel = MSR_F15H_PERF_CTL; + x86_pmu.perfctr = MSR_F15H_PERF_CTR; + x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE; + +- printk(KERN_INFO "perf: AMD core performance counters detected\n"); +- ++ pr_cont("core perfctr, "); + return 0; + } + + __init int amd_pmu_init(void) + { ++ int ret; ++ + /* Performance-monitoring supported from K7 and later: */ + if (boot_cpu_data.x86 < 6) + return -ENODEV; + + x86_pmu = amd_pmu; + +- setup_event_constraints(); +- setup_perfctr_core(); ++ ret = amd_core_pmu_init(); ++ if (ret) ++ return ret; + + /* Events are common for all AMDs */ + memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, diff --git a/queue-3.10/series b/queue-3.10/series index d8349c71350..1bd602ddfc0 100644 --- a/queue-3.10/series +++ b/queue-3.10/series @@ -9,3 +9,6 @@ ipr-fix-invalid-array-indexing-for-hrrq.patch xhci-fix-off-by-one-error-in-trb-dma-address-boundary-check.patch usb-sierra-add-1199-68ab-device-id.patch md-use-kzalloc-when-bitmap-is-disabled.patch +ipmi-fix-timeout-calculation-when-bmc-is-disconnected.patch +mfd-sm501-dbg_regs-attribute-must-be-read-only.patch +perf-x86-amd-rework-amd-pmu-init-code.patch