From: Paolo Bonzini Date: Sat, 25 May 2024 08:03:22 +0000 (+0200) Subject: target/i386: no single-step exception after MOV or POP SS X-Git-Tag: v7.2.12~11 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f417712ef156235b96c2c15a1ad7e3dfe5542695;p=thirdparty%2Fqemu.git target/i386: no single-step exception after MOV or POP SS Intel SDM 18.3.1.4 "If an occurrence of the MOV or POP instruction loads the SS register executes with EFLAGS.TF = 1, no single-step debug exception occurs following the MOV or POP instruction." Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini (cherry picked from commit f0f0136abba688a6516647a79cc91e03fad6d5d7) Signed-off-by: Michael Tokarev (Mjt: context fixup for v8.1.0-1189-gad75a51e84af "tcg: Rename cpu_env to tcg_env") --- diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b4f25e2f59c..417bc26e8fa 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2833,7 +2833,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); tcg_gen_exit_tb(NULL, 0); - } else if (s->flags & HF_TF_MASK) { + } else if ((s->flags & HF_TF_MASK) && !inhibit) { gen_helper_single_step(cpu_env); } else if (jr && /* give irqs a chance to happen */