From: Kito Cheng <kito.cheng@sifive.com>
Date: Wed, 30 Mar 2022 08:19:00 +0000 (+0800)
Subject: RISC-V: Fixing -misa-spec [PR/target 104853]
X-Git-Tag: releases/gcc-11.3.0~144
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f41871dfdbd9d0c3368c0bc32d879fd5485e7abb;p=thirdparty%2Fgcc.git

RISC-V: Fixing -misa-spec [PR/target 104853]

gcc/ChangeLog:

	* config.gcc (riscv*-*-*): Set right default isa spec.
---

diff --git a/gcc/config.gcc b/gcc/config.gcc
index d1a66cfe6e42..d69be8853bc1 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4632,6 +4632,7 @@ case "${target}" in
 		case "${with_isa_spec}" in
 		""|default|2.2)
 			tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_2P2"
+			with_isa_spec=2.2
 			;;
 		20191213 | 201912)
 			tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"