From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: Tue, 6 Apr 2021 20:26:21 +0000 (+0200)
Subject: target/mips: Fix TCG temporary leak in gen_cache_operation()
X-Git-Tag: v6.0.0-rc3~5^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f4349ba966abfe39f5d98694abd7c7551d5c8c02;p=thirdparty%2Fqemu.git

target/mips: Fix TCG temporary leak in gen_cache_operation()

Fix a TCG temporary leak when translating CACHE opcode.

Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210406202857.1440744-1-f4bug@amsat.org>
---

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c518bf3963b..71fa5ec1973 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
     TCGv t1 = tcg_temp_new();
     gen_base_offset_addr(ctx, t1, base, offset);
     gen_helper_cache(cpu_env, t1, t0);
+    tcg_temp_free(t1);
+    tcg_temp_free_i32(t0);
 }
 
 #if defined(TARGET_MIPS64)