From: Ryan Wanner Date: Thu, 27 Feb 2025 15:52:02 +0000 (-0700) Subject: ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC X-Git-Tag: v6.15-rc1~159^2~13^2~6 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f4573d25c14d1ccd7401bc5fcd56eb76811df418;p=thirdparty%2Fkernel%2Flinux.git ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC Add Reset Controller support to SAMA7D65 SoC. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/a9620ff11456a1ddfb9c289421606602193ce5b6.1740671156.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 92a5347e35b59..b614747374bd8 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -77,6 +77,13 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>;