From: Greg Kroah-Hartman Date: Fri, 7 Feb 2014 04:23:33 +0000 (-0800) Subject: 3.4-stable patches X-Git-Tag: v3.4.80~77 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f49049fb3ac6adf3bcd95e40b61240890ef4b1ac;p=thirdparty%2Fkernel%2Fstable-queue.git 3.4-stable patches added patches: acpi-init-flag-use-of-acpi-and-acpi-idioms-for-power-supplies-to-regulator-api.patch slub-fix-calculation-of-cpu-slabs.patch turbostat-use-gcc-s-cpuid-functions-to-support-pic.patch --- diff --git a/queue-3.4/acpi-init-flag-use-of-acpi-and-acpi-idioms-for-power-supplies-to-regulator-api.patch b/queue-3.4/acpi-init-flag-use-of-acpi-and-acpi-idioms-for-power-supplies-to-regulator-api.patch new file mode 100644 index 00000000000..bd4e68487f7 --- /dev/null +++ b/queue-3.4/acpi-init-flag-use-of-acpi-and-acpi-idioms-for-power-supplies-to-regulator-api.patch @@ -0,0 +1,66 @@ +From 49a12877d2777cadcb838981c3c4f5a424aef310 Mon Sep 17 00:00:00 2001 +From: Mark Brown +Date: Mon, 27 Jan 2014 00:32:14 +0000 +Subject: ACPI / init: Flag use of ACPI and ACPI idioms for power supplies to regulator API + +From: Mark Brown + +commit 49a12877d2777cadcb838981c3c4f5a424aef310 upstream. + +There is currently no facility in ACPI to express the hookup of voltage +regulators, the expectation is that the regulators that exist in the +system will be handled transparently by firmware if they need software +control at all. This means that if for some reason the regulator API is +enabled on such a system it should assume that any supplies that devices +need are provided by the system at all relevant times without any software +intervention. + +Tell the regulator core to make this assumption by calling +regulator_has_full_constraints(). Do this as soon as we know we are using +ACPI so that the information is available to the regulator core as early +as possible. This will cause the regulator core to pretend that there is +an always on regulator supplying any supply that is requested but that has +not otherwise been mapped which is the behaviour expected on a system with +ACPI. + +Should the ability to specify regulators be added in future revisions of +ACPI then once we have support for ACPI mappings in the kernel the same +assumptions will apply. It is also likely that systems will default to a +mode of operation which does not require any interpretation of these +mappings in order to be compatible with existing operating system releases +so it should remain safe to make these assumptions even if the mappings +exist but are not supported by the kernel. + +Signed-off-by: Mark Brown +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/acpi/bus.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/acpi/bus.c ++++ b/drivers/acpi/bus.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #ifdef CONFIG_X86 + #include + #endif +@@ -921,6 +922,14 @@ void __init acpi_early_init(void) + goto error0; + } + ++ /* ++ * If the system is using ACPI then we can be reasonably ++ * confident that any regulators are managed by the firmware ++ * so tell the regulator core it has everything it needs to ++ * know. ++ */ ++ regulator_has_full_constraints(); ++ + return; + + error0: diff --git a/queue-3.4/series b/queue-3.4/series index bf7d46006e2..77fe8eeff6b 100644 --- a/queue-3.4/series +++ b/queue-3.4/series @@ -3,3 +3,6 @@ ftrace-have-function-graph-only-trace-based-on-global_ops-filters.patch intel-iommu-fix-off-by-one-in-pagetable-freeing.patch audit-correct-a-type-mismatch-in-audit_syscall_exit.patch mmc-atmel-mci-fix-timeout-errors-in-sdio-mode-when-using-dma.patch +slub-fix-calculation-of-cpu-slabs.patch +turbostat-use-gcc-s-cpuid-functions-to-support-pic.patch +acpi-init-flag-use-of-acpi-and-acpi-idioms-for-power-supplies-to-regulator-api.patch diff --git a/queue-3.4/slub-fix-calculation-of-cpu-slabs.patch b/queue-3.4/slub-fix-calculation-of-cpu-slabs.patch new file mode 100644 index 00000000000..760d12e97f0 --- /dev/null +++ b/queue-3.4/slub-fix-calculation-of-cpu-slabs.patch @@ -0,0 +1,54 @@ +From 8afb1474db4701d1ab80cd8251137a3260e6913e Mon Sep 17 00:00:00 2001 +From: Li Zefan +Date: Tue, 10 Sep 2013 11:43:37 +0800 +Subject: slub: Fix calculation of cpu slabs + +From: Li Zefan + +commit 8afb1474db4701d1ab80cd8251137a3260e6913e upstream. + + /sys/kernel/slab/:t-0000048 # cat cpu_slabs + 231 N0=16 N1=215 + /sys/kernel/slab/:t-0000048 # cat slabs + 145 N0=36 N1=109 + +See, the number of slabs is smaller than that of cpu slabs. + +The bug was introduced by commit 49e2258586b423684f03c278149ab46d8f8b6700 +("slub: per cpu cache for partial pages"). + +We should use page->pages instead of page->pobjects when calculating +the number of cpu partial slabs. This also fixes the mapping of slabs +and nodes. + +As there's no variable storing the number of total/active objects in +cpu partial slabs, and we don't have user interfaces requiring those +statistics, I just add WARN_ON for those cases. + +Acked-by: Christoph Lameter +Reviewed-by: Wanpeng Li +Signed-off-by: Li Zefan +Signed-off-by: Pekka Enberg +Signed-off-by: Greg Kroah-Hartman + +--- + mm/slub.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/mm/slub.c ++++ b/mm/slub.c +@@ -4520,7 +4520,13 @@ static ssize_t show_slab_objects(struct + page = c->partial; + + if (page) { +- x = page->pobjects; ++ node = page_to_nid(page); ++ if (flags & SO_TOTAL) ++ WARN_ON_ONCE(1); ++ else if (flags & SO_OBJECTS) ++ WARN_ON_ONCE(1); ++ else ++ x = page->pages; + total += x; + nodes[node] += x; + } diff --git a/queue-3.4/turbostat-use-gcc-s-cpuid-functions-to-support-pic.patch b/queue-3.4/turbostat-use-gcc-s-cpuid-functions-to-support-pic.patch new file mode 100644 index 00000000000..a3a6c37996b --- /dev/null +++ b/queue-3.4/turbostat-use-gcc-s-cpuid-functions-to-support-pic.patch @@ -0,0 +1,88 @@ +From 2b92865e648ce04a39fda4f903784a5d01ecb0dc Mon Sep 17 00:00:00 2001 +From: Josh Triplett +Date: Tue, 20 Aug 2013 17:20:14 -0700 +Subject: turbostat: Use GCC's CPUID functions to support PIC +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Josh Triplett + +commit 2b92865e648ce04a39fda4f903784a5d01ecb0dc upstream. + +turbostat uses inline assembly to call cpuid. On 32-bit x86, on systems +that have certain security features enabled by default that make -fPIC +the default, this causes a build error: + +turbostat.c: In function ‘check_cpuid’: +turbostat.c:1906:2: error: PIC register clobbered by ‘ebx’ in ‘asm’ + asm("cpuid" : "=a" (fms), "=c" (ecx), "=d" (edx) : "a" (1) : "ebx"); + ^ + +GCC provides a header cpuid.h, containing a __get_cpuid function that +works with both PIC and non-PIC. (On PIC, it saves and restores ebx +around the cpuid instruction.) Use that instead. + +Signed-off-by: Josh Triplett +Signed-off-by: Len Brown +Signed-off-by: Greg Kroah-Hartman + +--- + tools/power/x86/turbostat/turbostat.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +--- a/tools/power/x86/turbostat/turbostat.c ++++ b/tools/power/x86/turbostat/turbostat.c +@@ -34,6 +34,7 @@ + #include + #include + #include ++#include + + #define MSR_TSC 0x10 + #define MSR_NEHALEM_PLATFORM_INFO 0xCE +@@ -932,7 +933,7 @@ void check_cpuid() + + eax = ebx = ecx = edx = 0; + +- asm("cpuid" : "=a" (max_level), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (0)); ++ __get_cpuid(0, &max_level, &ebx, &ecx, &edx); + + if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) + genuine_intel = 1; +@@ -941,7 +942,7 @@ void check_cpuid() + fprintf(stderr, "%.4s%.4s%.4s ", + (char *)&ebx, (char *)&edx, (char *)&ecx); + +- asm("cpuid" : "=a" (fms), "=c" (ecx), "=d" (edx) : "a" (1) : "ebx"); ++ __get_cpuid(1, &fms, &ebx, &ecx, &edx); + family = (fms >> 8) & 0xf; + model = (fms >> 4) & 0xf; + stepping = fms & 0xf; +@@ -963,7 +964,7 @@ void check_cpuid() + * This check is valid for both Intel and AMD. + */ + ebx = ecx = edx = 0; +- asm("cpuid" : "=a" (max_level), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (0x80000000)); ++ __get_cpuid(0x80000000, &max_level, &ebx, &ecx, &edx); + + if (max_level < 0x80000007) { + fprintf(stderr, "CPUID: no invariant TSC (max_level 0x%x)\n", max_level); +@@ -974,7 +975,7 @@ void check_cpuid() + * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 + * this check is valid for both Intel and AMD + */ +- asm("cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (0x80000007)); ++ __get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx); + has_invariant_tsc = edx & (1 << 8); + + if (!has_invariant_tsc) { +@@ -987,7 +988,7 @@ void check_cpuid() + * this check is valid for both Intel and AMD + */ + +- asm("cpuid" : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (0x6)); ++ __get_cpuid(0x6, &eax, &ebx, &ecx, &edx); + has_aperf = ecx & (1 << 0); + if (!has_aperf) { + fprintf(stderr, "No APERF MSR\n");