From: Greg Kroah-Hartman Date: Mon, 15 Nov 2021 13:01:08 +0000 (+0100) Subject: 5.14-stable patches X-Git-Tag: v5.4.160~60 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f602be646522050330024a81a15f7cdcc1076d3b;p=thirdparty%2Fkernel%2Fstable-queue.git 5.14-stable patches added patches: arm-9155-1-fix-early-early_iounmap.patch arm-9156-1-drop-cc-option-fallbacks-for-architecture-selection.patch mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch mips-fix-duplicated-slashes-for-platform-file-path.patch parisc-fix-backtrace-to-always-include-init-funtion-names.patch parisc-flush-kernel-data-mapping-in-set_pte_at-when-installing-pte-for-user-page.patch smb3-do-not-error-on-fsync-when-readonly.patch x86-mce-add-errata-workaround-for-skylake-skx37.patch --- diff --git a/queue-5.14/arm-9155-1-fix-early-early_iounmap.patch b/queue-5.14/arm-9155-1-fix-early-early_iounmap.patch new file mode 100644 index 00000000000..0e8b393c4d8 --- /dev/null +++ b/queue-5.14/arm-9155-1-fix-early-early_iounmap.patch @@ -0,0 +1,40 @@ +From 0d08e7bf0d0d1a29aff7b16ef516f7415eb1aa05 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= +Date: Thu, 4 Nov 2021 17:28:28 +0100 +Subject: ARM: 9155/1: fix early early_iounmap() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Michał Mirosław + +commit 0d08e7bf0d0d1a29aff7b16ef516f7415eb1aa05 upstream. + +Currently __set_fixmap() bails out with a warning when called in early boot +from early_iounmap(). Fix it, and while at it, make the comment a bit easier +to understand. + +Cc: +Fixes: b089c31c519c ("ARM: 8667/3: Fix memory attribute inconsistencies when using fixmap") +Acked-by: Ard Biesheuvel +Signed-off-by: Michał Mirosław +Signed-off-by: Russell King (Oracle) +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/mm/mmu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/mm/mmu.c ++++ b/arch/arm/mm/mmu.c +@@ -390,9 +390,9 @@ void __set_fixmap(enum fixed_addresses i + BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START); + BUG_ON(idx >= __end_of_fixed_addresses); + +- /* we only support device mappings until pgprot_kernel has been set */ ++ /* We support only device mappings before pgprot_kernel is set. */ + if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && +- pgprot_val(pgprot_kernel) == 0)) ++ pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0)) + return; + + if (pgprot_val(prot)) diff --git a/queue-5.14/arm-9156-1-drop-cc-option-fallbacks-for-architecture-selection.patch b/queue-5.14/arm-9156-1-drop-cc-option-fallbacks-for-architecture-selection.patch new file mode 100644 index 00000000000..576bbd1c165 --- /dev/null +++ b/queue-5.14/arm-9156-1-drop-cc-option-fallbacks-for-architecture-selection.patch @@ -0,0 +1,103 @@ +From 418ace9992a7647c446ed3186df40cf165b67298 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Sat, 6 Nov 2021 19:42:29 +0100 +Subject: ARM: 9156/1: drop cc-option fallbacks for architecture selection + +From: Arnd Bergmann + +commit 418ace9992a7647c446ed3186df40cf165b67298 upstream. + +Naresh and Antonio ran into a build failure with latest Debian +armhf compilers, with lots of output like + + tmp/ccY3nOAs.s:2215: Error: selected processor does not support `cpsid i' in ARM mode + +As it turns out, $(cc-option) fails early here when the FPU is not +selected before CPU architecture is selected, as the compiler +option check runs before enabling -msoft-float, which causes +a problem when testing a target architecture level without an FPU: + +cc1: error: '-mfloat-abi=hard': selected architecture lacks an FPU + +Passing e.g. -march=armv6k+fp in place of -march=armv6k would avoid this +issue, but the fallback logic is already broken because all supported +compilers (gcc-5 and higher) are much more recent than these options, +and building with -march=armv5t as a fallback no longer works. + +The best way forward that I see is to just remove all the checks, which +also has the nice side-effect of slightly improving the startup time for +'make'. + +The -mtune=marvell-f option was apparently never supported by any mainline +compiler, and the custom Codesourcery gcc build that did support is +now too old to build kernels, so just use -mtune=xscale unconditionally +for those. + +This should be safe to apply on all stable kernels, and will be required +in order to keep building them with gcc-11 and higher. + +Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=996419 + +Reported-by: Antonio Terceiro +Reported-by: Naresh Kamboju +Reported-by: Sebastian Andrzej Siewior +Tested-by: Sebastian Reichel +Tested-by: Klaus Kudielka +Cc: Matthias Klose +Cc: stable@vger.kernel.org +Signed-off-by: Arnd Bergmann +Signed-off-by: Russell King (Oracle) +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/Makefile | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -60,15 +60,15 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i + # Note that GCC does not numerically define an architecture version + # macro, but instead defines a whole series of macros which makes + # testing for a specific architecture or later rather impossible. +-arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m +-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) +-arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) ++arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m ++arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a ++arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6 + # Only override the compiler option if ARMv6. The ARMv6K extensions are + # always available in ARMv7 + ifeq ($(CONFIG_CPU_32v6),y) +-arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k) ++arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 -march=armv6k + endif +-arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t) ++arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 -march=armv5te + arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t + arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4 + arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m +@@ -82,7 +82,7 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7t + tune-$(CONFIG_CPU_ARM740T) =-mtune=arm7tdmi + tune-$(CONFIG_CPU_ARM9TDMI) =-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM940T) =-mtune=arm9tdmi +-tune-$(CONFIG_CPU_ARM946E) =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi) ++tune-$(CONFIG_CPU_ARM946E) =-mtune=arm9e + tune-$(CONFIG_CPU_ARM920T) =-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM922T) =-mtune=arm9tdmi + tune-$(CONFIG_CPU_ARM925T) =-mtune=arm9tdmi +@@ -90,11 +90,11 @@ tune-$(CONFIG_CPU_ARM926T) =-mtune=arm9t + tune-$(CONFIG_CPU_FA526) =-mtune=arm9tdmi + tune-$(CONFIG_CPU_SA110) =-mtune=strongarm110 + tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 +-tune-$(CONFIG_CPU_XSCALE) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale +-tune-$(CONFIG_CPU_XSC3) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale +-tune-$(CONFIG_CPU_FEROCEON) =$(call cc-option,-mtune=marvell-f,-mtune=xscale) +-tune-$(CONFIG_CPU_V6) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) +-tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) ++tune-$(CONFIG_CPU_XSCALE) =-mtune=xscale ++tune-$(CONFIG_CPU_XSC3) =-mtune=xscale ++tune-$(CONFIG_CPU_FEROCEON) =-mtune=xscale ++tune-$(CONFIG_CPU_V6) =-mtune=arm1136j-s ++tune-$(CONFIG_CPU_V6K) =-mtune=arm1136j-s + + # Evaluate tune cc-option calls now + tune-y := $(tune-y) diff --git a/queue-5.14/mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch b/queue-5.14/mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch new file mode 100644 index 00000000000..5d948430986 --- /dev/null +++ b/queue-5.14/mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch @@ -0,0 +1,80 @@ +From a923a2676e60683aee46aa4b93c30aff240ac20d Mon Sep 17 00:00:00 2001 +From: "Maciej W. Rozycki" +Date: Fri, 22 Oct 2021 00:58:23 +0200 +Subject: MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL + +From: Maciej W. Rozycki + +commit a923a2676e60683aee46aa4b93c30aff240ac20d upstream. + +Fix assembly errors like: + +{standard input}: Assembler messages: +{standard input}:287: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32' +{standard input}:680: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32' +{standard input}:1274: Error: opcode not supported on this processor: mips3 (mips3) `dins $12,$9,32,32' +{standard input}:2175: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32' +make[1]: *** [scripts/Makefile.build:277: mm/highmem.o] Error 1 + +with code produced from `__cmpxchg64' for MIPS64r2 CPU configurations +using CONFIG_32BIT and CONFIG_PHYS_ADDR_T_64BIT. + +This is due to MIPS_ISA_ARCH_LEVEL downgrading the assembly architecture +to `r4000' i.e. MIPS III for MIPS64r2 configurations, while there is a +block of code containing a DINS MIPS64r2 instruction conditionalized on +MIPS_ISA_REV >= 2 within the scope of the downgrade. + +The assembly architecture override code pattern has been put there for +LL/SC instructions, so that code compiles for configurations that select +a processor to build for that does not support these instructions while +still providing run-time support for processors that do, dynamically +switched by non-constant `cpu_has_llsc'. It went in with linux-mips.org +commit aac8aa7717a2 ("Enable a suitable ISA for the assembler around +ll/sc so that code builds even for processors that don't support the +instructions. Plus minor formatting fixes.") back in 2005. + +Fix the problem by wrapping these instructions along with the adjacent +SYNC instructions only, following the practice established with commit +cfd54de3b0e4 ("MIPS: Avoid move psuedo-instruction whilst using +MIPS_ISA_LEVEL") and commit 378ed6f0e3c5 ("MIPS: Avoid using .set mips0 +to restore ISA"). Strictly speaking the SYNC instructions do not have +to be wrapped as they are only used as a Loongson3 erratum workaround, +so they will be enabled in the assembler by default, but do this so as +to keep code consistent with other places. + +Reported-by: kernel test robot +Signed-off-by: Maciej W. Rozycki +Fixes: c7e2d71dda7a ("MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()") +Cc: stable@vger.kernel.org # v5.1+ +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/include/asm/cmpxchg.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/arch/mips/include/asm/cmpxchg.h ++++ b/arch/mips/include/asm/cmpxchg.h +@@ -249,6 +249,7 @@ static inline unsigned long __cmpxchg64( + /* Load 64 bits from ptr */ + " " __SYNC(full, loongson3_war) " \n" + "1: lld %L0, %3 # __cmpxchg64 \n" ++ " .set pop \n" + /* + * Split the 64 bit value we loaded into the 2 registers that hold the + * ret variable. +@@ -276,12 +277,14 @@ static inline unsigned long __cmpxchg64( + " or %L1, %L1, $at \n" + " .set at \n" + # endif ++ " .set push \n" ++ " .set " MIPS_ISA_ARCH_LEVEL " \n" + /* Attempt to store new at ptr */ + " scd %L1, %2 \n" + /* If we failed, loop! */ + "\t" __SC_BEQZ "%L1, 1b \n" +- " .set pop \n" + "2: " __SYNC(full, loongson3_war) " \n" ++ " .set pop \n" + : "=&r"(ret), + "=&r"(tmp), + "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr) diff --git a/queue-5.14/mips-fix-duplicated-slashes-for-platform-file-path.patch b/queue-5.14/mips-fix-duplicated-slashes-for-platform-file-path.patch new file mode 100644 index 00000000000..c0b67e2117d --- /dev/null +++ b/queue-5.14/mips-fix-duplicated-slashes-for-platform-file-path.patch @@ -0,0 +1,37 @@ +From cca2aac8acf470b01066f559acd7146fc4c32ae8 Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada +Date: Wed, 10 Nov 2021 00:01:46 +0900 +Subject: MIPS: fix duplicated slashes for Platform file path + +From: Masahiro Yamada + +commit cca2aac8acf470b01066f559acd7146fc4c32ae8 upstream. + +platform-y accumulates platform names with a slash appended. +The current $(patsubst ...) ends up with doubling slashes. + +GNU Make still include Platform files, but in case of an error, +a clumsy file path is displayed: + + arch/mips/loongson2ef//Platform:36: *** only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop. Stop. + +Signed-off-by: Masahiro Yamada +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Jason Self +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/Makefile | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -254,7 +254,9 @@ endif + # + # Board-dependent options and extra files + # ++ifdef need-compiler + include arch/mips/Kbuild.platforms ++endif + + ifdef CONFIG_PHYSICAL_START + load-y = $(CONFIG_PHYSICAL_START) diff --git a/queue-5.14/parisc-fix-backtrace-to-always-include-init-funtion-names.patch b/queue-5.14/parisc-fix-backtrace-to-always-include-init-funtion-names.patch new file mode 100644 index 00000000000..031df618379 --- /dev/null +++ b/queue-5.14/parisc-fix-backtrace-to-always-include-init-funtion-names.patch @@ -0,0 +1,57 @@ +From 279917e27edc293eb645a25428c6ab3f3bca3f86 Mon Sep 17 00:00:00 2001 +From: Helge Deller +Date: Thu, 4 Nov 2021 20:19:00 +0100 +Subject: parisc: Fix backtrace to always include init funtion names + +From: Helge Deller + +commit 279917e27edc293eb645a25428c6ab3f3bca3f86 upstream. + +I noticed that sometimes at kernel startup the backtraces did not +included the function names of init functions. Their address were not +resolved to function names and instead only the address was printed. + +Debugging shows that the culprit is is_ksym_addr() which is called +by the backtrace functions to check if an address belongs to a function in +the kernel. The problem occurs only for CONFIG_KALLSYMS_ALL=y. + +When looking at is_ksym_addr() one can see that for CONFIG_KALLSYMS_ALL=y +the function only tries to resolve the address via is_kernel() function, +which checks like this: + if (addr >= _stext && addr <= _end) + return 1; +On parisc the init functions are located before _stext, so this check fails. +Other platforms seem to have all functions (including init functions) +behind _stext. + +The following patch moves the _stext symbol at the beginning of the +kernel and thus includes the init section. This fixes the check and does +not seem to have any negative side effects on where the kernel mapping +happens in the map_pages() function in arch/parisc/mm/init.c. + +Signed-off-by: Helge Deller +Cc: stable@kernel.org # 5.4+ +Signed-off-by: Greg Kroah-Hartman +--- + arch/parisc/kernel/vmlinux.lds.S | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/parisc/kernel/vmlinux.lds.S ++++ b/arch/parisc/kernel/vmlinux.lds.S +@@ -57,6 +57,8 @@ SECTIONS + { + . = KERNEL_BINARY_TEXT_START; + ++ _stext = .; /* start of kernel text, includes init code & data */ ++ + __init_begin = .; + HEAD_TEXT_SECTION + MLONGCALL_DISCARD(INIT_TEXT_SECTION(8)) +@@ -80,7 +82,6 @@ SECTIONS + /* freed after init ends here */ + + _text = .; /* Text and read-only data */ +- _stext = .; + MLONGCALL_KEEP(INIT_TEXT_SECTION(8)) + .text ALIGN(PAGE_SIZE) : { + TEXT_TEXT diff --git a/queue-5.14/parisc-flush-kernel-data-mapping-in-set_pte_at-when-installing-pte-for-user-page.patch b/queue-5.14/parisc-flush-kernel-data-mapping-in-set_pte_at-when-installing-pte-for-user-page.patch new file mode 100644 index 00000000000..7789591bdbc --- /dev/null +++ b/queue-5.14/parisc-flush-kernel-data-mapping-in-set_pte_at-when-installing-pte-for-user-page.patch @@ -0,0 +1,93 @@ +From 38860b2c8bb1b92f61396eb06a63adff916fc31d Mon Sep 17 00:00:00 2001 +From: John David Anglin +Date: Mon, 8 Nov 2021 16:48:16 -0500 +Subject: parisc: Flush kernel data mapping in set_pte_at() when installing pte for user page + +From: John David Anglin + +commit 38860b2c8bb1b92f61396eb06a63adff916fc31d upstream. + +For years, there have been random segmentation faults in userspace on +SMP PA-RISC machines. It occurred to me that this might be a problem in +set_pte_at(). MIPS and some other architectures do cache flushes when +installing PTEs with the present bit set. + +Here I have adapted the code in update_mmu_cache() to flush the kernel +mapping when the kernel flush is deferred, or when the kernel mapping +may alias with the user mapping. This simplifies calls to +update_mmu_cache(). + +I also changed the barrier in set_pte() from a compiler barrier to a +full memory barrier. I know this change is not sufficient to fix the +problem. It might not be needed. + +I have had a few days of operation with 5.14.16 to 5.15.1 and haven't +seen any random segmentation faults on rp3440 or c8000 so far. + +Signed-off-by: John David Anglin +Signed-off-by: Helge Deller +Cc: stable@kernel.org # 5.12+ +Signed-off-by: Greg Kroah-Hartman +--- + arch/parisc/include/asm/pgtable.h | 10 ++++++++-- + arch/parisc/kernel/cache.c | 4 ++-- + 2 files changed, 10 insertions(+), 4 deletions(-) + +--- a/arch/parisc/include/asm/pgtable.h ++++ b/arch/parisc/include/asm/pgtable.h +@@ -76,6 +76,8 @@ static inline void purge_tlb_entries(str + purge_tlb_end(flags); + } + ++extern void __update_cache(pte_t pte); ++ + /* Certain architectures need to do special things when PTEs + * within a page table are directly modified. Thus, the following + * hook is made available. +@@ -83,11 +85,14 @@ static inline void purge_tlb_entries(str + #define set_pte(pteptr, pteval) \ + do { \ + *(pteptr) = (pteval); \ +- barrier(); \ ++ mb(); \ + } while(0) + + #define set_pte_at(mm, addr, pteptr, pteval) \ + do { \ ++ if (pte_present(pteval) && \ ++ pte_user(pteval)) \ ++ __update_cache(pteval); \ + *(pteptr) = (pteval); \ + purge_tlb_entries(mm, addr); \ + } while (0) +@@ -303,6 +308,7 @@ extern unsigned long *empty_zero_page; + + #define pte_none(x) (pte_val(x) == 0) + #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) ++#define pte_user(x) (pte_val(x) & _PAGE_USER) + #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0)) + + #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) +@@ -410,7 +416,7 @@ extern void paging_init (void); + + #define PG_dcache_dirty PG_arch_1 + +-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); ++#define update_mmu_cache(vms,addr,ptep) __update_cache(*ptep) + + /* Encode and de-code a swap entry */ + +--- a/arch/parisc/kernel/cache.c ++++ b/arch/parisc/kernel/cache.c +@@ -83,9 +83,9 @@ EXPORT_SYMBOL(flush_cache_all_local); + #define pfn_va(pfn) __va(PFN_PHYS(pfn)) + + void +-update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) ++__update_cache(pte_t pte) + { +- unsigned long pfn = pte_pfn(*ptep); ++ unsigned long pfn = pte_pfn(pte); + struct page *page; + + /* We don't have pte special. As a result, we can be called with diff --git a/queue-5.14/series b/queue-5.14/series index ecd9610b9da..369b9c42172 100644 --- a/queue-5.14/series +++ b/queue-5.14/series @@ -784,3 +784,11 @@ vsock-prevent-unnecessary-refcnt-inc-for-nonblocking.patch net-smc-fix-sk_refcnt-underflow-on-linkdown-and-fall.patch cxgb4-fix-eeprom-len-when-diagnostics-not-implemente.patch selftests-net-udpgso_bench_rx-fix-port-argument.patch +smb3-do-not-error-on-fsync-when-readonly.patch +arm-9155-1-fix-early-early_iounmap.patch +arm-9156-1-drop-cc-option-fallbacks-for-architecture-selection.patch +parisc-fix-backtrace-to-always-include-init-funtion-names.patch +parisc-flush-kernel-data-mapping-in-set_pte_at-when-installing-pte-for-user-page.patch +mips-fix-duplicated-slashes-for-platform-file-path.patch +mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch +x86-mce-add-errata-workaround-for-skylake-skx37.patch diff --git a/queue-5.14/smb3-do-not-error-on-fsync-when-readonly.patch b/queue-5.14/smb3-do-not-error-on-fsync-when-readonly.patch new file mode 100644 index 00000000000..81efb79abb9 --- /dev/null +++ b/queue-5.14/smb3-do-not-error-on-fsync-when-readonly.patch @@ -0,0 +1,89 @@ +From 71e6864eacbef0b2645ca043cdfbac272cb6cea3 Mon Sep 17 00:00:00 2001 +From: Steve French +Date: Wed, 10 Nov 2021 01:47:48 -0600 +Subject: smb3: do not error on fsync when readonly + +From: Steve French + +commit 71e6864eacbef0b2645ca043cdfbac272cb6cea3 upstream. + +Linux allows doing a flush/fsync on a file open for read-only, +but the protocol does not allow that. If the file passed in +on the flush is read-only try to find a writeable handle for +the same inode, if that is not possible skip sending the +fsync call to the server to avoid breaking the apps. + +Reported-by: Julian Sikorski +Tested-by: Julian Sikorski +Suggested-by: Jeremy Allison +Reviewed-by: Paulo Alcantara (SUSE) +Signed-off-by: Steve French +Signed-off-by: Greg Kroah-Hartman +--- + fs/cifs/file.c | 35 +++++++++++++++++++++++++++++------ + 1 file changed, 29 insertions(+), 6 deletions(-) + +--- a/fs/cifs/file.c ++++ b/fs/cifs/file.c +@@ -2689,12 +2689,23 @@ int cifs_strict_fsync(struct file *file, + tcon = tlink_tcon(smbfile->tlink); + if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NOSSYNC)) { + server = tcon->ses->server; +- if (server->ops->flush) +- rc = server->ops->flush(xid, tcon, &smbfile->fid); +- else ++ if (server->ops->flush == NULL) { + rc = -ENOSYS; ++ goto strict_fsync_exit; ++ } ++ ++ if ((OPEN_FMODE(smbfile->f_flags) & FMODE_WRITE) == 0) { ++ smbfile = find_writable_file(CIFS_I(inode), FIND_WR_ANY); ++ if (smbfile) { ++ rc = server->ops->flush(xid, tcon, &smbfile->fid); ++ cifsFileInfo_put(smbfile); ++ } else ++ cifs_dbg(FYI, "ignore fsync for file not open for write\n"); ++ } else ++ rc = server->ops->flush(xid, tcon, &smbfile->fid); + } + ++strict_fsync_exit: + free_xid(xid); + return rc; + } +@@ -2706,6 +2717,7 @@ int cifs_fsync(struct file *file, loff_t + struct cifs_tcon *tcon; + struct TCP_Server_Info *server; + struct cifsFileInfo *smbfile = file->private_data; ++ struct inode *inode = file_inode(file); + struct cifs_sb_info *cifs_sb = CIFS_FILE_SB(file); + + rc = file_write_and_wait_range(file, start, end); +@@ -2722,12 +2734,23 @@ int cifs_fsync(struct file *file, loff_t + tcon = tlink_tcon(smbfile->tlink); + if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NOSSYNC)) { + server = tcon->ses->server; +- if (server->ops->flush) +- rc = server->ops->flush(xid, tcon, &smbfile->fid); +- else ++ if (server->ops->flush == NULL) { + rc = -ENOSYS; ++ goto fsync_exit; ++ } ++ ++ if ((OPEN_FMODE(smbfile->f_flags) & FMODE_WRITE) == 0) { ++ smbfile = find_writable_file(CIFS_I(inode), FIND_WR_ANY); ++ if (smbfile) { ++ rc = server->ops->flush(xid, tcon, &smbfile->fid); ++ cifsFileInfo_put(smbfile); ++ } else ++ cifs_dbg(FYI, "ignore fsync for file not open for write\n"); ++ } else ++ rc = server->ops->flush(xid, tcon, &smbfile->fid); + } + ++fsync_exit: + free_xid(xid); + return rc; + } diff --git a/queue-5.14/x86-mce-add-errata-workaround-for-skylake-skx37.patch b/queue-5.14/x86-mce-add-errata-workaround-for-skylake-skx37.patch new file mode 100644 index 00000000000..7f66c92618c --- /dev/null +++ b/queue-5.14/x86-mce-add-errata-workaround-for-skylake-skx37.patch @@ -0,0 +1,43 @@ +From e629fc1407a63dbb748f828f9814463ffc2a0af0 Mon Sep 17 00:00:00 2001 +From: Dave Jones +Date: Fri, 29 Oct 2021 16:57:59 -0400 +Subject: x86/mce: Add errata workaround for Skylake SKX37 + +From: Dave Jones + +commit e629fc1407a63dbb748f828f9814463ffc2a0af0 upstream. + +Errata SKX37 is word-for-word identical to the other errata listed in +this workaround. I happened to notice this after investigating a CMCI +storm on a Skylake host. While I can't confirm this was the root cause, +spurious corrected errors does sound like a likely suspect. + +Fixes: 2976908e4198 ("x86/mce: Do not log spurious corrected mce errors") +Signed-off-by: Dave Jones +Signed-off-by: Dave Hansen +Reviewed-by: Tony Luck +Cc: +Link: https://lkml.kernel.org/r/20211029205759.GA7385@codemonkey.org.uk +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/mce/intel.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/cpu/mce/intel.c ++++ b/arch/x86/kernel/cpu/mce/intel.c +@@ -547,12 +547,13 @@ bool intel_filter_mce(struct mce *m) + { + struct cpuinfo_x86 *c = &boot_cpu_data; + +- /* MCE errata HSD131, HSM142, HSW131, BDM48, and HSM142 */ ++ /* MCE errata HSD131, HSM142, HSW131, BDM48, HSM142 and SKX37 */ + if ((c->x86 == 6) && + ((c->x86_model == INTEL_FAM6_HASWELL) || + (c->x86_model == INTEL_FAM6_HASWELL_L) || + (c->x86_model == INTEL_FAM6_BROADWELL) || +- (c->x86_model == INTEL_FAM6_HASWELL_G)) && ++ (c->x86_model == INTEL_FAM6_HASWELL_G) || ++ (c->x86_model == INTEL_FAM6_SKYLAKE_X)) && + (m->bank == 0) && + ((m->status & 0xa0000000ffffffff) == 0x80000000000f0005)) + return true;