From: Greg Kroah-Hartman Date: Sun, 22 Apr 2018 08:22:56 +0000 (+0200) Subject: 3.18-stable patches X-Git-Tag: v3.18.106~36 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f62a3bbe0dcfd1dbb8fb75894b597db9c31dc291;p=thirdparty%2Fkernel%2Fstable-queue.git 3.18-stable patches added patches: drm-radeon-fix-pcie-lane-width-calculation.patch --- diff --git a/queue-3.18/drm-radeon-fix-pcie-lane-width-calculation.patch b/queue-3.18/drm-radeon-fix-pcie-lane-width-calculation.patch new file mode 100644 index 00000000000..832450078d9 --- /dev/null +++ b/queue-3.18/drm-radeon-fix-pcie-lane-width-calculation.patch @@ -0,0 +1,47 @@ +From 85e290d92b4b794d0c758c53007eb4248d385386 Mon Sep 17 00:00:00 2001 +From: Paul Parsons +Date: Sat, 2 Apr 2016 12:32:30 +0100 +Subject: drm/radeon: Fix PCIe lane width calculation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Paul Parsons + +commit 85e290d92b4b794d0c758c53007eb4248d385386 upstream. + +Two years ago I tried an AMD Radeon E8860 embedded GPU with the drm driver. +The dmesg output included driver warnings about an invalid PCIe lane width. +Tracking the problem back led to si_set_pcie_lane_width_in_smc(). +The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and +ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting +value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. +Applying the increment silenced the warnings. +The code has not changed since, so either my analysis was incorrect or the +bug has gone unnoticed. Hence submitting this as an RFC. + +Acked-by: Christian König +Acked-by: Chunming Zhou +Signed-off-by: Paul Parsons +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/si_dpm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/si_dpm.c ++++ b/drivers/gpu/drm/radeon/si_dpm.c +@@ -5894,9 +5894,9 @@ static void si_set_pcie_lane_width_in_sm + { + u32 lane_width; + u32 new_lane_width = +- (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; ++ ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; + u32 current_lane_width = +- (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; ++ ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; + + if (new_lane_width != current_lane_width) { + radeon_set_pcie_lanes(rdev, new_lane_width); diff --git a/queue-3.18/series b/queue-3.18/series index 649b61484c6..46942da0d48 100644 --- a/queue-3.18/series +++ b/queue-3.18/series @@ -37,3 +37,4 @@ alsa-pcm-fix-endless-loop-for-xrun-recovery-in-oss-emulation.patch ext4-add-validity-checks-for-bitmap-block-numbers.patch ext4-fail-ext4_iget-for-root-directory-if-unallocated.patch ext4-don-t-allow-r-w-mounts-if-metadata-blocks-overlap-the-superblock.patch +drm-radeon-fix-pcie-lane-width-calculation.patch