From: Daniel Henrique Barboza Date: Tue, 21 Jan 2025 17:06:25 +0000 (-0300) Subject: target/riscv/debug.c: use wp size = 4 for 32-bit CPUs X-Git-Tag: v7.2.17~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f7703cc6a7d7d2ce46f02b4e146ada3d807a5150;p=thirdparty%2Fqemu.git target/riscv/debug.c: use wp size = 4 for 32-bit CPUs The mcontrol select bit (19) is always zero, meaning our triggers will always match virtual addresses. In this condition, if the user does not specify a size for the trigger, the access size defaults to XLEN. At this moment we're using def_size = 8 regardless of CPU XLEN. Use def_size = 4 in case we're running 32 bits. Fixes: 95799e36c1 ("target/riscv: Add initial support for the Sdtrig extension") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250121170626.1992570-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis (cherry picked from commit 3fba76e61caa46329afc399b3ecaaba70c8b0a4e) Signed-off-by: Michael Tokarev --- diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 26ea764407..cf71b52899 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -305,7 +305,7 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) bool enabled = type2_breakpoint_enabled(ctrl); CPUState *cs = env_cpu(env); int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; - uint32_t size; + uint32_t size, def_size; if (!enabled) { return; @@ -328,7 +328,9 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) cpu_watchpoint_insert(cs, addr, size, flags, &env->cpu_watchpoint[index]); } else { - cpu_watchpoint_insert(cs, addr, 8, flags, + def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; + + cpu_watchpoint_insert(cs, addr, def_size, flags, &env->cpu_watchpoint[index]); } }