From: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Date: Mon, 8 Jan 2024 14:32:58 +0000 (+0000)
Subject: hw/arm: add cache controller for Freescale i.MX6
X-Git-Tag: v9.0.0-rc0~112^2~40
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f7f5784af19155df658237d1aae04297d371402b;p=thirdparty%2Fqemu.git

hw/arm: add cache controller for Freescale i.MX6

Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231219105510.4907-1-n.ostrenkov@gmail.com
[PMM: fixed stray whitespace]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 660f49db498..b853577e725 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -537,6 +537,7 @@ config FSL_IMX6
     select IMX_I2C
     select IMX_USBPHY
     select WDT_IMX2
+    select PL310  # cache controller
     select SDHCI
 
 config ASPEED_SOC
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index b2153022c04..af2e982b052 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -154,6 +154,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
     }
 
+    /* L2 cache controller */
+    sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL);
+
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
         return;
     }