From: Claudiu Beznea Date: Thu, 19 Nov 2020 15:43:14 +0000 (+0200) Subject: clk: at91: sama7g5: decrease lower limit for MCK0 rate X-Git-Tag: v5.11-rc1~44^2~1^5~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f803858af84e1e6916edfbc5ae0fac403c02ee46;p=thirdparty%2Flinux.git clk: at91: sama7g5: decrease lower limit for MCK0 rate On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is also changed by DVFS to avoid over/under clocking of MCK0 consumers. The lower limit is changed to be able to set MCK0 accordingly by DVFS. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 335e9c943c651..29d9781e67122 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -807,7 +807,7 @@ static const struct clk_pll_characteristics pll_characteristics = { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, + .output = { .min = 50000000, .max = 200000000 }, .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, };