From: Maxime Ripard Date: Thu, 3 Sep 2020 08:00:56 +0000 (+0200) Subject: drm/vc4: hvs: Make sure our channel is reset X-Git-Tag: v5.10-rc1~123^2~10^2~192 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f8b13d9bcc674efa3af2d75414fa612936a5a2ea;p=thirdparty%2Flinux.git drm/vc4: hvs: Make sure our channel is reset In order to clear our intermediate FIFOs that might end up with a stale pixel, let's make sure our FIFO channel is reset every time our channel is setup. Signed-off-by: Maxime Ripard Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Reviewed-by: Dave Stevenson Link: https://patchwork.freedesktop.org/patch/msgid/b34c562b36177c758dd2e9d84bceb07689bfbe05.1599120059.git-series.maxime@cerno.tech --- diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index efaae60bb3231..0f56a7b579168 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, u32 dispbkgndx; u32 dispctrl; + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + /* Turn on the scaler, which will wait for vstart to start * compositing. * When feeding the transposer, we should operate in oneshot