From: Greg Kroah-Hartman Date: Mon, 10 Feb 2025 13:30:51 +0000 (+0100) Subject: 6.1-stable patches X-Git-Tag: v6.6.77~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=f9d2e787d14137f178e6b98e2ffcd2c78a5609af;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch --- diff --git a/queue-6.1/clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch b/queue-6.1/clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch new file mode 100644 index 0000000000..d5edf0b9a7 --- /dev/null +++ b/queue-6.1/clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch @@ -0,0 +1,81 @@ +From 33f1722eb86e45320a3dd7b3d42f6593a1d595c2 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Mon, 21 Oct 2024 19:32:48 +0200 +Subject: clk: qcom: clk-alpha-pll: fix alpha mode configuration + +From: Gabor Juhos + +commit 33f1722eb86e45320a3dd7b3d42f6593a1d595c2 upstream. + +Commit c45ae598fc16 ("clk: qcom: support for alpha mode configuration") +added support for configuring alpha mode, but it seems that the feature +was never working in practice. + +The value of the alpha_{en,mode}_mask members of the configuration gets +added to the value parameter passed to the regmap_update_bits() function, +however the same values are not getting applied to the bitmask. As the +result, the respective bits in the USER_CTL register are never modifed +which leads to improper configuration of several PLLs. + +The following table shows the PLL configurations where the 'alpha_en_mask' +member is set and which are passed as a parameter for the +clk_alpha_pll_configure() function. In the table the 'expected rate' column +shows the rate the PLL should run at with the given configuration, and +the 'real rate' column shows the rate the PLL runs at actually. The real +rates has been verified on hardwareOn IPQ* platforms, on other platforms, +those are computed values only. + + file pll expected rate real rate + dispcc-qcm2290.c disp_cc_pll0 768.0 MHz 768.0 MHz + dispcc-sm6115.c disp_cc_pll0 768.0 MHz 768.0 MHz + gcc-ipq5018.c ubi32_pll 1000.0 MHz != 984.0 MHz + gcc-ipq6018.c nss_crypto_pll 1200.0 MHz 1200.0 MHz + gcc-ipq6018.c ubi32_pll 1497.6 MHz != 1488.0 MHz + gcc-ipq8074.c nss_crypto_pll 1200.0 MHz != 1190.4 MHz + gcc-qcm2290.c gpll11 532.0 MHz != 518.4 MHz + gcc-qcm2290.c gpll8 533.2 MHz != 518.4 MHz + gcc-qcs404.c gpll3 921.6 MHz 921.6 MHz + gcc-sm6115.c gpll11 600.0 MHz != 595.2 MHz + gcc-sm6115.c gpll8 800.0 MHz != 787.2 MHz + gpucc-sdm660.c gpu_cc_pll0 800.0 MHz != 787.2 MHz + gpucc-sdm660.c gpu_cc_pll1 740.0 MHz != 729.6 MHz + gpucc-sm6115.c gpu_cc_pll0 1200.0 MHz != 1190.4 MHz + gpucc-sm6115.c gpu_cc_pll1 640.0 MHz != 633.6 MHz + gpucc-sm6125.c gpu_pll0 1020.0 MHz != 1017.6 MHz + gpucc-sm6125.c gpu_pll1 930.0 MHz != 921.6 MHz + mmcc-sdm660.c mmpll8 930.0 MHz != 921.6 MHz + mmcc-sdm660.c mmpll5 825.0 MHz != 806.4 MHz + +As it can be seen from the above, there are several PLLs which are +configured incorrectly. + +Change the code to apply both 'alpha_en_mask' and 'alpha_mode_mask' +values to the bitmask in order to configure the alpha mode correctly. + +Applying the 'alpha_en_mask' fixes the initial rate of the PLLs showed +in the table above. Since the 'alpha_mode_mask' is not used by any driver +currently, that part of the change causes no functional changes. + +Cc: stable@vger.kernel.org +Fixes: c45ae598fc16 ("clk: qcom: support for alpha mode configuration") +Signed-off-by: Gabor Juhos +Reviewed-by: Dmitry Baryshkov +Tested-by: Gabor Juhos +Link: https://lore.kernel.org/r/20241021-fix-alpha-mode-config-v1-1-f32c254e02bc@gmail.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -339,6 +339,8 @@ void clk_alpha_pll_configure(struct clk_ + mask |= config->pre_div_mask; + mask |= config->post_div_mask; + mask |= config->vco_mask; ++ mask |= config->alpha_en_mask; ++ mask |= config->alpha_mode_mask; + + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + diff --git a/queue-6.1/clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch b/queue-6.1/clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch new file mode 100644 index 0000000000..f3a3f3f926 --- /dev/null +++ b/queue-6.1/clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch @@ -0,0 +1,37 @@ +From 89aa5925d201b90a48416784831916ca203658f9 Mon Sep 17 00:00:00 2001 +From: Anastasia Belova +Date: Tue, 3 Dec 2024 11:42:31 +0300 +Subject: clk: qcom: clk-rpmh: prevent integer overflow in recalc_rate + +From: Anastasia Belova + +commit 89aa5925d201b90a48416784831916ca203658f9 upstream. + +aggr_state and unit fields are u32. The result of their +multiplication may not fit in this type. + +Add explicit casting to prevent overflow. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 04053f4d23a4 ("clk: qcom: clk-rpmh: Add IPA clock support") +Cc: stable@vger.kernel.org # 5.4+ +Signed-off-by: Anastasia Belova +Link: https://lore.kernel.org/r/20241203084231.6001-1-abelova@astralinux.ru +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-rpmh.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/clk-rpmh.c ++++ b/drivers/clk/qcom/clk-rpmh.c +@@ -332,7 +332,7 @@ static unsigned long clk_rpmh_bcm_recalc + { + struct clk_rpmh *c = to_clk_rpmh(hw); + +- return c->aggr_state * c->unit; ++ return (unsigned long)c->aggr_state * c->unit; + } + + static const struct clk_ops clk_rpmh_bcm_ops = { diff --git a/queue-6.1/clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch b/queue-6.1/clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch new file mode 100644 index 0000000000..ec303aa903 --- /dev/null +++ b/queue-6.1/clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch @@ -0,0 +1,58 @@ +From d4cdb196f182d2fbe336c968228be00d8c3fed05 Mon Sep 17 00:00:00 2001 +From: Luca Weiss +Date: Fri, 20 Dec 2024 10:03:31 +0100 +Subject: clk: qcom: dispcc-sm6350: Add missing parent_map for a clock + +From: Luca Weiss + +commit d4cdb196f182d2fbe336c968228be00d8c3fed05 upstream. + +If a clk_rcg2 has a parent, it should also have parent_map defined, +otherwise we'll get a NULL pointer dereference when calling clk_set_rate +like the following: + + [ 3.388105] Call trace: + [ 3.390664] qcom_find_src_index+0x3c/0x70 (P) + [ 3.395301] qcom_find_src_index+0x1c/0x70 (L) + [ 3.399934] _freq_tbl_determine_rate+0x48/0x100 + [ 3.404753] clk_rcg2_determine_rate+0x1c/0x28 + [ 3.409387] clk_core_determine_round_nolock+0x58/0xe4 + [ 3.421414] clk_core_round_rate_nolock+0x48/0xfc + [ 3.432974] clk_core_round_rate_nolock+0xd0/0xfc + [ 3.444483] clk_core_set_rate_nolock+0x8c/0x300 + [ 3.455886] clk_set_rate+0x38/0x14c + +Add the parent_map property for the clock where it's missing and also +un-inline the parent_data as well to keep the matching parent_map and +parent_data together. + +Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") +Cc: stable@vger.kernel.org +Signed-off-by: Luca Weiss +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-2-64f3d04cb2eb@fairphone.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/dispcc-sm6350.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/dispcc-sm6350.c ++++ b/drivers/clk/qcom/dispcc-sm6350.c +@@ -187,13 +187,12 @@ static struct clk_rcg2 disp_cc_mdss_dp_a + .cmd_rcgr = 0x1144, + .mnd_width = 0, + .hid_width = 5, ++ .parent_map = disp_cc_parent_map_6, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", +- .parent_data = &(const struct clk_parent_data){ +- .fw_name = "bi_tcxo", +- }, +- .num_parents = 1, ++ .parent_data = disp_cc_parent_data_6, ++ .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), + .ops = &clk_rcg2_ops, + }, + }; diff --git a/queue-6.1/clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch b/queue-6.1/clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch new file mode 100644 index 0000000000..0b1f498e86 --- /dev/null +++ b/queue-6.1/clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch @@ -0,0 +1,33 @@ +From 88d9dca36aac9659446be1e569d8fbe3462b5741 Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Fri, 20 Dec 2024 15:20:48 +0530 +Subject: clk: qcom: gcc-mdm9607: Fix cmd_rcgr offset for blsp1_uart6 rcg + +From: Satya Priya Kakitapalli + +commit 88d9dca36aac9659446be1e569d8fbe3462b5741 upstream. + +Fix cmd_rcgr offset for blsp1_uart6_apps_clk_src on mdm9607 platform. + +Fixes: 48b7253264ea ("clk: qcom: Add MDM9607 GCC driver") +Cc: stable@vger.kernel.org +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20241220095048.248425-1-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/gcc-mdm9607.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/gcc-mdm9607.c ++++ b/drivers/clk/qcom/gcc-mdm9607.c +@@ -536,7 +536,7 @@ static struct clk_rcg2 blsp1_uart5_apps_ + }; + + static struct clk_rcg2 blsp1_uart6_apps_clk_src = { +- .cmd_rcgr = 0x6044, ++ .cmd_rcgr = 0x7044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, diff --git a/queue-6.1/clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch b/queue-6.1/clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch new file mode 100644 index 0000000000..5a4209f8b1 --- /dev/null +++ b/queue-6.1/clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch @@ -0,0 +1,90 @@ +From 96fe1a7ee477d701cfc98ab9d3c730c35d966861 Mon Sep 17 00:00:00 2001 +From: Luca Weiss +Date: Fri, 20 Dec 2024 10:03:30 +0100 +Subject: clk: qcom: gcc-sm6350: Add missing parent_map for two clocks + +From: Luca Weiss + +commit 96fe1a7ee477d701cfc98ab9d3c730c35d966861 upstream. + +If a clk_rcg2 has a parent, it should also have parent_map defined, +otherwise we'll get a NULL pointer dereference when calling clk_set_rate +like the following: + + [ 3.388105] Call trace: + [ 3.390664] qcom_find_src_index+0x3c/0x70 (P) + [ 3.395301] qcom_find_src_index+0x1c/0x70 (L) + [ 3.399934] _freq_tbl_determine_rate+0x48/0x100 + [ 3.404753] clk_rcg2_determine_rate+0x1c/0x28 + [ 3.409387] clk_core_determine_round_nolock+0x58/0xe4 + [ 3.421414] clk_core_round_rate_nolock+0x48/0xfc + [ 3.432974] clk_core_round_rate_nolock+0xd0/0xfc + [ 3.444483] clk_core_set_rate_nolock+0x8c/0x300 + [ 3.455886] clk_set_rate+0x38/0x14c + +Add the parent_map property for two clocks where it's missing and also +un-inline the parent_data as well to keep the matching parent_map and +parent_data together. + +Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") +Cc: stable@vger.kernel.org +Signed-off-by: Luca Weiss +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-1-64f3d04cb2eb@fairphone.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/gcc-sm6350.c | 22 ++++++++++++++-------- + 1 file changed, 14 insertions(+), 8 deletions(-) + +--- a/drivers/clk/qcom/gcc-sm6350.c ++++ b/drivers/clk/qcom/gcc-sm6350.c +@@ -182,6 +182,14 @@ static const struct clk_parent_data gcc_ + { .hw = &gpll0_out_odd.clkr.hw }, + }; + ++static const struct parent_map gcc_parent_map_3[] = { ++ { P_BI_TCXO, 0 }, ++}; ++ ++static const struct clk_parent_data gcc_parent_data_3[] = { ++ { .fw_name = "bi_tcxo" }, ++}; ++ + static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +@@ -701,13 +709,12 @@ static struct clk_rcg2 gcc_ufs_phy_phy_a + .cmd_rcgr = 0x3a0b0, + .mnd_width = 0, + .hid_width = 5, ++ .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", +- .parent_data = &(const struct clk_parent_data){ +- .fw_name = "bi_tcxo", +- }, +- .num_parents = 1, ++ .parent_data = gcc_parent_data_3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, + }; +@@ -764,13 +771,12 @@ static struct clk_rcg2 gcc_usb30_prim_mo + .cmd_rcgr = 0x1a034, + .mnd_width = 0, + .hid_width = 5, ++ .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", +- .parent_data = &(const struct clk_parent_data){ +- .fw_name = "bi_tcxo", +- }, +- .num_parents = 1, ++ .parent_data = gcc_parent_data_3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, + }; diff --git a/queue-6.1/clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch b/queue-6.1/clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch new file mode 100644 index 0000000000..cad89b820c --- /dev/null +++ b/queue-6.1/clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch @@ -0,0 +1,59 @@ +From 16414720045de30945b8d14b7907e0cbf81a4b49 Mon Sep 17 00:00:00 2001 +From: Cody Eksal +Date: Fri, 8 Nov 2024 20:37:37 -0400 +Subject: clk: sunxi-ng: a100: enable MMC clock reparenting + +From: Cody Eksal + +commit 16414720045de30945b8d14b7907e0cbf81a4b49 upstream. + +While testing the MMC nodes proposed in [1], it was noted that mmc0/1 +would fail to initialize, with "mmc: fatal err update clk timeout" in +the kernel logs. A closer look at the clock definitions showed that the MMC +MPs had the "CLK_SET_RATE_NO_REPARENT" flag set. No reason was given for +adding this flag in the first place, and its original purpose is unknown, +but it doesn't seem to make sense and results in severe limitations to MMC +speeds. Thus, remove this flag from the 3 MMC MPs. + +[1] https://msgid.link/20241024170540.2721307-10-masterr3c0rd@epochal.quest + +Fixes: fb038ce4db55 ("clk: sunxi-ng: add support for the Allwinner A100 CCU") +Cc: stable@vger.kernel.org +Signed-off-by: Cody Eksal +Reviewed-by: Andre Przywara +Link: https://patch.msgid.link/20241109003739.3440904-1-masterr3c0rd@epochal.quest +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c +@@ -436,7 +436,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI + 24, 2, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ +- CLK_SET_RATE_NO_REPARENT); ++ 0); + + static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, + 0, 4, /* M */ +@@ -444,7 +444,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI + 24, 2, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ +- CLK_SET_RATE_NO_REPARENT); ++ 0); + + static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, + 0, 4, /* M */ +@@ -452,7 +452,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI + 24, 2, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ +- CLK_SET_RATE_NO_REPARENT); ++ 0); + + static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); + static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); diff --git a/queue-6.1/series b/queue-6.1/series index eb933f0d4c..57d29c634e 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -356,3 +356,9 @@ drm-komeda-add-check-for-komeda_get_layer_fourcc_list.patch drm-i915-drop-64bpp-yuv-formats-from-icl-sdr-planes.patch bluetooth-l2cap-handle-null-sock-pointer-in-l2cap_sock_alloc.patch bluetooth-l2cap-accept-zero-as-a-special-value-for-mtu-auto-selection.patch +clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch +clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch +clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch +clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch +clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch +clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch