From: David S. Miller Date: Wed, 12 Oct 2011 22:32:23 +0000 (+0000) Subject: Fix sparc when assembler lacks support for vis3/fmaf instructions. X-Git-Tag: releases/gcc-4.7.0~3179 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fad034a7605150489b6435a7e4719c3e40bd0539;p=thirdparty%2Fgcc.git Fix sparc when assembler lacks support for vis3/fmaf instructions. gcc/ * config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF to zero when assembler lacks support for such instructions. * config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3 and MASK_FMAF in defaults when assembler lacks necessary support. gcc/testsuite/ * gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify '-mvis3' instead of 'mcpu=niagara3' in options. * gcc.target/sparc/fhalve.c: Likewise. * gcc.target/sparc/fnegop.c: Likewise. * gcc.target/sparc/fpadds.c: Likewise. * gcc.target/sparc/fshift.c: Likewise. * gcc.target/sparc/fucmp.c: Likewise. * gcc.target/sparc/lzd.c: Likewise. * gcc.target/sparc/vis3misc.c: Likewise. * gcc.target/sparc/xmul.c: Likewise. From-SVN: r179875 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cdc939122d00..017594f98dfa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-10-12 David S. Miller + + * config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF + to zero when assembler lacks support for such instructions. + * config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3 + and MASK_FMAF in defaults when assembler lacks necessary support. + 2011-10-12 Jakub Jelinek * config/i386/sse.md (vec_unpacks_lo_, diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 9c7cc56b43e0..fa790b359d2a 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -850,7 +850,11 @@ sparc_option_override (void) cpu = &cpu_table[(int) sparc_cpu_and_features]; target_flags &= ~cpu->disable; - target_flags |= cpu->enable; + target_flags |= (cpu->enable +#ifndef HAVE_AS_FMAF_HPC_VIS3 + & ~(MASK_FMAF | MASK_VIS3) +#endif + ); /* If -mfpu or -mno-fpu was explicitly used, don't override with the processor default. */ diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 0642ff2f9e8a..669f106fe326 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1871,10 +1871,6 @@ extern int sparc_indent_opcode; #ifndef HAVE_AS_FMAF_HPC_VIS3 #define AS_NIAGARA3_FLAG "b" -#undef TARGET_FMAF -#define TARGET_FMAF 0 -#undef TARGET_VIS3 -#define TARGET_VIS3 0 #else #define AS_NIAGARA3_FLAG "d" #endif diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9e8f1f9b952a..943f36f4ab08 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2011-10-12 David S. Miller + + * gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify + '-mvis3' instead of 'mcpu=niagara3' in options. + * gcc.target/sparc/fhalve.c: Likewise. + * gcc.target/sparc/fnegop.c: Likewise. + * gcc.target/sparc/fpadds.c: Likewise. + * gcc.target/sparc/fshift.c: Likewise. + * gcc.target/sparc/fucmp.c: Likewise. + * gcc.target/sparc/lzd.c: Likewise. + * gcc.target/sparc/vis3misc.c: Likewise. + * gcc.target/sparc/xmul.c: Likewise. + 2011-10-12 Eric Botcazou * gnat.dg/vect1.ad[sb]: New test. diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c index 989274c68584..d1be910f5e0b 100644 --- a/gcc/testsuite/gcc.target/sparc/cmask.c +++ b/gcc/testsuite/gcc.target/sparc/cmask.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ void test_cm8 (long x) { diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c index 737fc71bbcf6..b8f0745afc98 100644 --- a/gcc/testsuite/gcc.target/sparc/fhalve.c +++ b/gcc/testsuite/gcc.target/sparc/fhalve.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ float test_fhadds (float x, float y) { diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c index 3e3e72c820ca..cbdf28f4c601 100644 --- a/gcc/testsuite/gcc.target/sparc/fnegop.c +++ b/gcc/testsuite/gcc.target/sparc/fnegop.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mvis3" } */ float test_fnadds(float x, float y) { diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c index f55cb057a2ad..9b1027d5fcab 100644 --- a/gcc/testsuite/gcc.target/sparc/fpadds.c +++ b/gcc/testsuite/gcc.target/sparc/fpadds.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ typedef int __v2si __attribute__((vector_size(8))); typedef int __v1si __attribute__((vector_size(4))); typedef short __v4hi __attribute__((vector_size(8))); diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c index 6adbed691719..1f032151c16b 100644 --- a/gcc/testsuite/gcc.target/sparc/fshift.c +++ b/gcc/testsuite/gcc.target/sparc/fshift.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ typedef int __v2si __attribute__((vector_size(8))); typedef short __v4hi __attribute__((vector_size(8))); diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c index 4e7ecadcd4ae..6e8f1b3418ef 100644 --- a/gcc/testsuite/gcc.target/sparc/fucmp.c +++ b/gcc/testsuite/gcc.target/sparc/fucmp.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ typedef unsigned char vec8 __attribute__((vector_size(8))); long test_fucmple8 (vec8 a, vec8 b) diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c index 5ffaf56e5584..bc2b8522be8a 100644 --- a/gcc/testsuite/gcc.target/sparc/lzd.c +++ b/gcc/testsuite/gcc.target/sparc/lzd.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ int test_clz(int a) { return __builtin_clz(a); diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c index e3ef49e210d3..7286d705dd56 100644 --- a/gcc/testsuite/gcc.target/sparc/vis3misc.c +++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ typedef int __v2si __attribute__((vector_size(8))); typedef short __v4hi __attribute__((vector_size(8))); typedef unsigned char __v8qi __attribute__((vector_size(8))); diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c index 5d249d092dbc..a432ee1fec1d 100644 --- a/gcc/testsuite/gcc.target/sparc/xmul.c +++ b/gcc/testsuite/gcc.target/sparc/xmul.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { vis3 } } } */ -/* { dg-options "-mcpu=niagara3 -mvis" } */ +/* { dg-do compile } */ +/* { dg-options "-mvis3" } */ typedef long long int64_t; int64_t test_umulxhi (int64_t x, int64_t y)