From: Philippe Mathieu-Daudé Date: Fri, 29 Jan 2021 13:23:19 +0000 (+0800) Subject: hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled X-Git-Tag: v6.0.0-rc0~112^2~11 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fb116b5456c818ae7c3b788adcbc05dfa416c90c;p=thirdparty%2Fqemu.git hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Ignore all other registers write except ECSPI_CONREG when the block is disabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Bin Meng Reviewed-by: Peter Maydell Message-id: 20210129132323.30946-7-bmeng.cn@gmail.com Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> Signed-off-by: Bin Meng Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 21e2c9dea3e..4cfbb73e35e 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -332,6 +332,14 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), (uint32_t)value); + if (!imx_spi_is_enabled(s)) { + /* Block is disabled */ + if (index != ECSPI_CONREG) { + /* Ignore access */ + return; + } + } + change_mask = s->regs[index] ^ value; switch (index) { @@ -340,10 +348,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, TYPE_IMX_SPI, __func__); break; case ECSPI_TXDATA: - if (!imx_spi_is_enabled(s)) { - /* Ignore writes if device is disabled */ - break; - } else if (fifo32_is_full(&s->tx_fifo)) { + if (fifo32_is_full(&s->tx_fifo)) { /* Ignore writes if queue is full */ break; }