From: Greg Kroah-Hartman Date: Fri, 7 Jul 2017 13:52:12 +0000 (+0200) Subject: 4.9-stable patches X-Git-Tag: v4.9.37~24 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fb1c61b157770357d2df583c48940a7de91a4353;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: pinctrl-cherryview-add-a-quirk-to-make-acer-chromebook-keyboard-work-again.patch pinctrl-cherryview-add-terminate-entry-for-dmi_system_id-tables.patch pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch pinctrl-qcom-ipq4019-add-missing-pingroups-for-pins-70.patch pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch pinctrl-sh-pfc-r8a7791-add-missing-hscif1-pinmux-data.patch pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch pinctrl-sh-pfc-r8a7794-swap-ata-signals.patch pinctrl-sh-pfc-r8a7795-fix-hscif2_clk_b-and-hscif4_ctrl.patch pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch pinctrl-stm32-fix-bad-function-call.patch pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch sysctl-don-t-print-negative-flag-for-proc_douintvec.patch sysctl-report-einval-if-value-is-larger-than-uint_max-for-proc_douintvec.patch --- diff --git a/queue-4.9/pinctrl-cherryview-add-a-quirk-to-make-acer-chromebook-keyboard-work-again.patch b/queue-4.9/pinctrl-cherryview-add-a-quirk-to-make-acer-chromebook-keyboard-work-again.patch new file mode 100644 index 00000000000..b17d6e88046 --- /dev/null +++ b/queue-4.9/pinctrl-cherryview-add-a-quirk-to-make-acer-chromebook-keyboard-work-again.patch @@ -0,0 +1,96 @@ +From 7036502783729c2aaf7a3c24c89087c58721430f Mon Sep 17 00:00:00 2001 +From: Mika Westerberg +Date: Mon, 10 Apr 2017 13:16:33 +0300 +Subject: pinctrl: cherryview: Add a quirk to make Acer Chromebook keyboard work again + +From: Mika Westerberg + +commit 7036502783729c2aaf7a3c24c89087c58721430f upstream. + +After commit 47c950d10202 ("pinctrl: cherryview: Do not add all +southwest and north GPIOs to IRQ domain") the driver does not add all +GPIOs to the irqdomain. The reason for that is that those GPIOs cannot +generate IRQs at all, only GPEs (General Purpose Events). This causes +Linux virtual IRQ numbering to change. + +However, it seems some CYAN Chromebooks, including Acer Chromebook +hardcodes these Linux IRQ numbers in the ACPI tables of the machine. +Since the numbering is different now, the IRQ meant for keyboard does +not match the Linux virtual IRQ number anymore making the keyboard +non-functional. + +Work this around by adding special quirk just for these machines where +we add back all GPIOs to the irqdomain. Rest of the Cherryview/Braswell +based machines will not be affected by the change. + +Link: https://bugzilla.kernel.org/show_bug.cgi?id=194945 +Fixes: 47c950d10202 ("pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain") +Reported-by: Adam S Levy +Signed-off-by: Mika Westerberg +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/intel/pinctrl-cherryview.c | 26 ++++++++++++++++++++++++-- + 1 file changed, 24 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/intel/pinctrl-cherryview.c ++++ b/drivers/pinctrl/intel/pinctrl-cherryview.c +@@ -13,6 +13,7 @@ + * published by the Free Software Foundation. + */ + ++#include + #include + #include + #include +@@ -1524,10 +1525,31 @@ static void chv_gpio_irq_handler(struct + chained_irq_exit(chip, desc); + } + ++/* ++ * Certain machines seem to hardcode Linux IRQ numbers in their ACPI ++ * tables. Since we leave GPIOs that are not capable of generating ++ * interrupts out of the irqdomain the numbering will be different and ++ * cause devices using the hardcoded IRQ numbers fail. In order not to ++ * break such machines we will only mask pins from irqdomain if the machine ++ * is not listed below. ++ */ ++static const struct dmi_system_id chv_no_valid_mask[] = { ++ { ++ /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ ++ .ident = "Acer Chromebook (CYAN)", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "Edgar"), ++ DMI_MATCH(DMI_BIOS_DATE, "05/21/2016"), ++ }, ++ } ++}; ++ + static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) + { + const struct chv_gpio_pinrange *range; + struct gpio_chip *chip = &pctrl->chip; ++ bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); + int ret, i, offset; + + *chip = chv_gpio_chip; +@@ -1536,7 +1558,7 @@ static int chv_gpio_probe(struct chv_pin + chip->label = dev_name(pctrl->dev); + chip->parent = pctrl->dev; + chip->base = -1; +- chip->irq_need_valid_mask = true; ++ chip->irq_need_valid_mask = need_valid_mask; + + ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); + if (ret) { +@@ -1567,7 +1589,7 @@ static int chv_gpio_probe(struct chv_pin + intsel &= CHV_PADCTRL0_INTSEL_MASK; + intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; + +- if (intsel >= pctrl->community->nirqs) ++ if (need_valid_mask && intsel >= pctrl->community->nirqs) + clear_bit(i, chip->irq_valid_mask); + } + diff --git a/queue-4.9/pinctrl-cherryview-add-terminate-entry-for-dmi_system_id-tables.patch b/queue-4.9/pinctrl-cherryview-add-terminate-entry-for-dmi_system_id-tables.patch new file mode 100644 index 00000000000..bf4f21339ec --- /dev/null +++ b/queue-4.9/pinctrl-cherryview-add-terminate-entry-for-dmi_system_id-tables.patch @@ -0,0 +1,34 @@ +From a9de080bbcd5c4e213a3d7bbb1e314d60980e943 Mon Sep 17 00:00:00 2001 +From: Wei Yongjun +Date: Tue, 25 Apr 2017 06:22:05 +0000 +Subject: pinctrl: cherryview: Add terminate entry for dmi_system_id tables + +From: Wei Yongjun + +commit a9de080bbcd5c4e213a3d7bbb1e314d60980e943 upstream. + +Make sure dmi_system_id tables are NULL terminated. + +Fixes: 703650278372 ("pinctrl: cherryview: Add a quirk to make Acer +Chromebook keyboard work again") +Signed-off-by: Wei Yongjun +Acked-by: Mika Westerberg +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/intel/pinctrl-cherryview.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/intel/pinctrl-cherryview.c ++++ b/drivers/pinctrl/intel/pinctrl-cherryview.c +@@ -1542,7 +1542,8 @@ static const struct dmi_system_id chv_no + DMI_MATCH(DMI_PRODUCT_NAME, "Edgar"), + DMI_MATCH(DMI_BIOS_DATE, "05/21/2016"), + }, +- } ++ }, ++ {} + }; + + static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) diff --git a/queue-4.9/pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch b/queue-4.9/pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch new file mode 100644 index 00000000000..eb062d403d1 --- /dev/null +++ b/queue-4.9/pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch @@ -0,0 +1,39 @@ +From 97ba26b8a9343008504d4e3a87d212bc07b05212 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 1 Apr 2017 15:59:21 +0200 +Subject: pinctrl: meson: meson8b: fix the NAND DQS pins + +From: Martin Blumenstingl + +commit 97ba26b8a9343008504d4e3a87d212bc07b05212 upstream. + +The nand_groups table uses different names for the NAND DQS pins than +the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). +This prevents using the NAND DQS pins in the devicetree. + +Fix this by ensuring that the GROUP() definition and the +meson8b_cbus_groups use the same name for these pins. + +Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b") +Signed-off-by: Martin Blumenstingl +Acked-by: Kevin Hilman +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/meson/pinctrl-meson8b.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/meson/pinctrl-meson8b.c ++++ b/drivers/pinctrl/meson/pinctrl-meson8b.c +@@ -739,8 +739,8 @@ static const char * const sdxc_c_groups[ + static const char * const nand_groups[] = { + "nand_io", "nand_io_ce0", "nand_io_ce1", + "nand_io_rb0", "nand_ale", "nand_cle", +- "nand_wen_clk", "nand_ren_clk", "nand_dqs0", +- "nand_dqs1" ++ "nand_wen_clk", "nand_ren_clk", "nand_dqs_0", ++ "nand_dqs_1" + }; + + static const char * const nor_groups[] = { diff --git a/queue-4.9/pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch b/queue-4.9/pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch new file mode 100644 index 00000000000..453b0aca3e4 --- /dev/null +++ b/queue-4.9/pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch @@ -0,0 +1,81 @@ +From da6c2addf66d7ff7d0b090d6267d4292f951e4e6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Thu, 18 May 2017 11:23:55 +0200 +Subject: pinctrl: mxs: atomically switch mux and drive strength config +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Uwe Kleine-König + +commit da6c2addf66d7ff7d0b090d6267d4292f951e4e6 upstream. + +To set the mux mode of a pin two bits must be set. Up to now this is +implemented using the following idiom: + + writel(mask, reg + CLR); + writel(value, reg + SET); + +. This however results in the mux mode being 0 between the two writes. + +On my machine there is an IC's reset pin connected to LCD_D20. The +bootloader configures this pin as GPIO output-high (i.e. not holding the +IC in reset). When Linux reconfigures the pin to GPIO the short time +LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse +the connected IC. + +The same problem is present for the pin's drive strength setting which is +reset to low drive strength before using the right value. + +So instead of relying on the hardware to modify the register setting +using two writes implement the bit toggling using read-modify-write. + +Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support") +Signed-off-by: Uwe Kleine-König +Acked-by: Shawn Guo +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/freescale/pinctrl-mxs.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +--- a/drivers/pinctrl/freescale/pinctrl-mxs.c ++++ b/drivers/pinctrl/freescale/pinctrl-mxs.c +@@ -194,6 +194,16 @@ static int mxs_pinctrl_get_func_groups(s + return 0; + } + ++static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg) ++{ ++ u32 tmp; ++ ++ tmp = readl(reg); ++ tmp &= ~(mask << shift); ++ tmp |= value << shift; ++ writel(tmp, reg); ++} ++ + static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) + { +@@ -211,8 +221,7 @@ static int mxs_pinctrl_set_mux(struct pi + reg += bank * 0x20 + pin / 16 * 0x10; + shift = pin % 16 * 2; + +- writel(0x3 << shift, reg + CLR); +- writel(g->muxsel[i] << shift, reg + SET); ++ mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg); + } + + return 0; +@@ -279,8 +288,7 @@ static int mxs_pinconf_group_set(struct + /* mA */ + if (config & MA_PRESENT) { + shift = pin % 8 * 4; +- writel(0x3 << shift, reg + CLR); +- writel(ma << shift, reg + SET); ++ mxs_pinctrl_rmwl(ma, 0x3, shift, reg); + } + + /* vol */ diff --git a/queue-4.9/pinctrl-qcom-ipq4019-add-missing-pingroups-for-pins-70.patch b/queue-4.9/pinctrl-qcom-ipq4019-add-missing-pingroups-for-pins-70.patch new file mode 100644 index 00000000000..7db35d64689 --- /dev/null +++ b/queue-4.9/pinctrl-qcom-ipq4019-add-missing-pingroups-for-pins-70.patch @@ -0,0 +1,62 @@ +From d7402de48efae57bbb0072e53d3800c30de57ea5 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Thu, 16 Mar 2017 21:36:07 +0100 +Subject: pinctrl: qcom: ipq4019: add missing pingroups for pins > 70 + +From: Christian Lamparter + +commit d7402de48efae57bbb0072e53d3800c30de57ea5 upstream. + +This patch adds the missing PINGROUP for GPIO70-99. +This fixes a crash that happens in pinctrl-msm, if any +of the GPIO70-99 are accessed. + +Fixes: 5303f7827fcd41d ("pinctrl: qcom: ipq4019: set ngpios to correct value") +Signed-off-by: Christian Lamparter +Acked-by: Bjorn Andersson +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/qcom/pinctrl-ipq4019.c | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c ++++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c +@@ -405,6 +405,36 @@ static const struct msm_pingroup ipq4019 + PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), ++ PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + }; + + static const struct msm_pinctrl_soc_data ipq4019_pinctrl = { diff --git a/queue-4.9/pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch b/queue-4.9/pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch new file mode 100644 index 00000000000..10a371d2e9f --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch @@ -0,0 +1,60 @@ +From 3908632fb829d73317c64c3d04f584b49f62e4ae Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov +Date: Wed, 29 Mar 2017 21:36:51 +0300 +Subject: pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal + +From: Sergei Shtylyov + +commit 3908632fb829d73317c64c3d04f584b49f62e4ae upstream. + +The R8A7791 PFC driver was apparently based on the preliminary revisions +of the user's manual, which omitted the DVC_MUTE signal altogether in +the PFC section. The modern manual has the signal described, so just add +the necassary data to the driver... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -203,7 +203,7 @@ enum { + + /* IPSR6 */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, +- FN_SCIF_CLK, FN_BPFCLK_E, ++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, +@@ -573,7 +573,7 @@ enum { + + /* IPSR6 */ + AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, +- SCIF_CLK_MARK, BPFCLK_E_MARK, ++ SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, + AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, + SCIFA2_RXD_MARK, FMIN_E_MARK, + AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, +@@ -1090,6 +1090,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), ++ PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), + PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), + PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), +@@ -5810,7 +5811,7 @@ static const struct pinmux_cfg_reg pinmu + 0, 0, + /* IP6_2_0 [3] */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, +- FN_SCIF_CLK, 0, FN_BPFCLK_E, ++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, diff --git a/queue-4.9/pinctrl-sh-pfc-r8a7791-add-missing-hscif1-pinmux-data.patch b/queue-4.9/pinctrl-sh-pfc-r8a7791-add-missing-hscif1-pinmux-data.patch new file mode 100644 index 00000000000..edc1cf26352 --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-r8a7791-add-missing-hscif1-pinmux-data.patch @@ -0,0 +1,50 @@ +From da7a692fbbab07f4e9798b5b52798f6e3256dd8f Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov +Date: Wed, 29 Mar 2017 21:36:50 +0300 +Subject: pinctrl: sh-pfc: r8a7791: Add missing HSCIF1 pinmux data + +From: Sergei Shtylyov + +commit da7a692fbbab07f4e9798b5b52798f6e3256dd8f upstream. + +The R8A7791 PFC driver was apparently based on the preliminary revisions +of the user's manual, which omitted the HSCIF1 group E signals in the +IPSR4 register description. This would cause HSCIF1's probe to fail with +the messages like below: + +sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989 +sh-sci e62c8000.serial: Error applying setting, reverse things back +sh-sci: probe of e62c8000.serial failed with error -22 + +Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E, +HCTS1#_E, and HRTS1#_E signals... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -1010,14 +1010,17 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), ++ PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), + PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), + PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), ++ PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4), + PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2), + PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), ++ PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4), + PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34), + PINMUX_IPSR_GPSR(IP4_20, SSI_WS34), + PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3), diff --git a/queue-4.9/pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch b/queue-4.9/pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch new file mode 100644 index 00000000000..475d9b4e7d9 --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch @@ -0,0 +1,32 @@ +From 58439280f84e6b39fd7d61f25ab30489c1aaf0a9 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov +Date: Thu, 30 Mar 2017 23:20:48 +0300 +Subject: pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux data + +From: Sergei Shtylyov + +commit 58439280f84e6b39fd7d61f25ab30489c1aaf0a9 upstream. + +PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong +1st argument -- most probably a result of cut&paste programming... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -1099,7 +1099,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT), + PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), +- PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0), ++ PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), + PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), diff --git a/queue-4.9/pinctrl-sh-pfc-r8a7794-swap-ata-signals.patch b/queue-4.9/pinctrl-sh-pfc-r8a7794-swap-ata-signals.patch new file mode 100644 index 00000000000..cf327d5efa7 --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-r8a7794-swap-ata-signals.patch @@ -0,0 +1,74 @@ +From 5f4c8cafe1148f8a91287072815df8f0b66f0e5c Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov +Date: Tue, 4 Apr 2017 23:20:16 +0300 +Subject: pinctrl: sh-pfc: r8a7794: Swap ATA signals + +From: Sergei Shtylyov + +commit 5f4c8cafe1148f8a91287072815df8f0b66f0e5c upstream. + +All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver +has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this. + +Fixes: 43c4436e2f18 ("pinctrl: sh-pfc: add R8A7794 PFC support") +Signed-off-by: Sergei Shtylyov +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +@@ -281,8 +281,8 @@ enum { + FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, + FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, + FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, +- FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, +- FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B, ++ FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, ++ FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B, + + /* IPSR13 */ + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, +@@ -575,8 +575,8 @@ enum { + ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, + VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, + SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, +- ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, +- VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK, ++ ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, ++ VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK, + + /* IPSR13 */ + SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, +@@ -1413,13 +1413,13 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1), + PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), +- PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N), ++ PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N), + PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2), + PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), +- PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N), ++ PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N), + PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), + + /* IPSR13 */ +@@ -4938,10 +4938,10 @@ static const struct pinmux_cfg_reg pinmu + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, +- FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0, ++ FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, + /* IP12_26_24 [3] */ + FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, +- FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0, ++ FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0, + /* IP12_23_21 [3] */ + FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, + FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, diff --git a/queue-4.9/pinctrl-sh-pfc-r8a7795-fix-hscif2_clk_b-and-hscif4_ctrl.patch b/queue-4.9/pinctrl-sh-pfc-r8a7795-fix-hscif2_clk_b-and-hscif4_ctrl.patch new file mode 100644 index 00000000000..642604ac46c --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-r8a7795-fix-hscif2_clk_b-and-hscif4_ctrl.patch @@ -0,0 +1,39 @@ +From 4324b6084f45b9faebda8d6563d8625d22b4b5df Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Sat, 11 Mar 2017 12:26:09 +0100 +Subject: pinctrl: sh-pfc: r8a7795: Fix hscif2_clk_b and hscif4_ctrl + +From: Geert Uytterhoeven + +commit 4324b6084f45b9faebda8d6563d8625d22b4b5df upstream. + +Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[]. + +Fixes: a56069c46c102710 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions") +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -2056,7 +2056,7 @@ static const unsigned int hscif2_clk_b_p + RCAR_GP_PIN(6, 21), + }; + static const unsigned int hscif2_clk_b_mux[] = { +- HSCK1_B_MARK, ++ HSCK2_B_MARK, + }; + static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ +@@ -2129,7 +2129,7 @@ static const unsigned int hscif4_ctrl_pi + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), + }; + static const unsigned int hscif4_ctrl_mux[] = { +- HRTS4_N_MARK, HCTS3_N_MARK, ++ HRTS4_N_MARK, HCTS4_N_MARK, + }; + + static const unsigned int hscif4_data_b_pins[] = { diff --git a/queue-4.9/pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch b/queue-4.9/pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch new file mode 100644 index 00000000000..49d84b1846c --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch @@ -0,0 +1,34 @@ +From 3091ae775fae17084013021d01513bc1ad274e6a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 9 Mar 2017 19:20:48 +0100 +Subject: pinctrl: sh-pfc: Update info pointer after SoC-specific init + +From: Geert Uytterhoeven + +commit 3091ae775fae17084013021d01513bc1ad274e6a upstream. + +Update the sh_pfc_soc_info pointer after calling the SoC-specific +initialization function, as it may have been updated to e.g. handle +different SoC revisions. This makes sure the correct subdriver name is +printed later. + +Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization") +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/core.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -586,6 +586,9 @@ static int sh_pfc_probe(struct platform_ + ret = info->ops->init(pfc); + if (ret < 0) + return ret; ++ ++ /* .init() may have overridden pfc->info */ ++ info = pfc->info; + } + + /* Enable dummy states for those platforms without pinctrl support */ diff --git a/queue-4.9/pinctrl-stm32-fix-bad-function-call.patch b/queue-4.9/pinctrl-stm32-fix-bad-function-call.patch new file mode 100644 index 00000000000..6b9c8513fe6 --- /dev/null +++ b/queue-4.9/pinctrl-stm32-fix-bad-function-call.patch @@ -0,0 +1,34 @@ +From b7c747d4627462f25b3daabf49c18895a6722faa Mon Sep 17 00:00:00 2001 +From: Alexandre TORGUE +Date: Tue, 30 May 2017 16:43:04 +0200 +Subject: pinctrl: stm32: Fix bad function call + +From: Alexandre TORGUE + +commit b7c747d4627462f25b3daabf49c18895a6722faa upstream. + +In stm32_pconf_parse_conf function, stm32_pmx_gpio_set_direction is +called with wrong parameter value. Indeed, using NULL value for range +will raise an oops. + +Fixes: aceb16dc2da5 ("pinctrl: Add STM32 MCUs support") +Reported-by: Dan Carpenter +Signed-off-by: Alexandre TORGUE +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/stm32/pinctrl-stm32.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/stm32/pinctrl-stm32.c ++++ b/drivers/pinctrl/stm32/pinctrl-stm32.c +@@ -798,7 +798,7 @@ static int stm32_pconf_parse_conf(struct + break; + case PIN_CONFIG_OUTPUT: + __stm32_gpio_set(bank, offset, arg); +- ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); ++ ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); + break; + default: + ret = -EINVAL; diff --git a/queue-4.9/pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch b/queue-4.9/pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch new file mode 100644 index 00000000000..c463ce2dfcf --- /dev/null +++ b/queue-4.9/pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch @@ -0,0 +1,37 @@ +From 7903d4f5e1dec53963cba9b1bc472a76a3532e07 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Mon, 22 May 2017 14:25:49 +0800 +Subject: pinctrl: sunxi: Fix SPDIF function name for A83T + +From: Chen-Yu Tsai + +commit 7903d4f5e1dec53963cba9b1bc472a76a3532e07 upstream. + +We use well known standard names for functions that have name, such as +I2C, SPI, SPDIF, etc.. + +Fix the function name of SPDIF, which was named OWA (One Wire Audio) +based on Allwinner datasheets. + +Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller + support") +Signed-off-by: Chen-Yu Tsai +Acked-by: Maxime Ripard +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +@@ -394,7 +394,7 @@ static const struct sunxi_desc_pin sun8i + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x3, "owa")), /* DOUT */ ++ SUNXI_FUNCTION(0x3, "spdif")), /* DOUT */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), diff --git a/queue-4.9/series b/queue-4.9/series index c2f939e12a4..31b9aa93c0f 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -12,3 +12,18 @@ usb-usbip-set-buffer-pointers-to-null-after-free.patch usb-fix-typo-in-the-definition-of-endpointrequest.patch usb-core-fix-device-node-leak.patch mac80211_hwsim-replace-bogus-hrtimer-clockid.patch +sysctl-don-t-print-negative-flag-for-proc_douintvec.patch +sysctl-report-einval-if-value-is-larger-than-uint_max-for-proc_douintvec.patch +pinctrl-qcom-ipq4019-add-missing-pingroups-for-pins-70.patch +pinctrl-cherryview-add-a-quirk-to-make-acer-chromebook-keyboard-work-again.patch +pinctrl-sh-pfc-r8a7794-swap-ata-signals.patch +pinctrl-sh-pfc-r8a7791-fix-scif2-pinmux-data.patch +pinctrl-sh-pfc-r8a7791-add-missing-dvc_mute-signal.patch +pinctrl-sh-pfc-r8a7795-fix-hscif2_clk_b-and-hscif4_ctrl.patch +pinctrl-meson-meson8b-fix-the-nand-dqs-pins.patch +pinctrl-stm32-fix-bad-function-call.patch +pinctrl-sunxi-fix-spdif-function-name-for-a83t.patch +pinctrl-cherryview-add-terminate-entry-for-dmi_system_id-tables.patch +pinctrl-mxs-atomically-switch-mux-and-drive-strength-config.patch +pinctrl-sh-pfc-r8a7791-add-missing-hscif1-pinmux-data.patch +pinctrl-sh-pfc-update-info-pointer-after-soc-specific-init.patch diff --git a/queue-4.9/sysctl-don-t-print-negative-flag-for-proc_douintvec.patch b/queue-4.9/sysctl-don-t-print-negative-flag-for-proc_douintvec.patch new file mode 100644 index 00000000000..8531d13ebeb --- /dev/null +++ b/queue-4.9/sysctl-don-t-print-negative-flag-for-proc_douintvec.patch @@ -0,0 +1,44 @@ +From 5380e5644afbba9e3d229c36771134976f05c91e Mon Sep 17 00:00:00 2001 +From: Liping Zhang +Date: Fri, 7 Apr 2017 23:51:06 +0800 +Subject: sysctl: don't print negative flag for proc_douintvec + +From: Liping Zhang + +commit 5380e5644afbba9e3d229c36771134976f05c91e upstream. + +I saw some very confusing sysctl output on my system: + # cat /proc/sys/net/core/xfrm_aevent_rseqth + -2 + # cat /proc/sys/net/core/xfrm_aevent_etime + -10 + # cat /proc/sys/net/ipv4/tcp_notsent_lowat + -4294967295 + +Because we forget to set the *negp flag in proc_douintvec, so it will +become a garbage value. + +Since the value related to proc_douintvec is always an unsigned integer, +so we can set *negp to false explictily to fix this issue. + +Fixes: e7d316a02f68 ("sysctl: handle error writing UINT_MAX to u32 fields") +Signed-off-by: Liping Zhang +Cc: Subash Abhinov Kasiviswanathan +Cc: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + kernel/sysctl.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/kernel/sysctl.c ++++ b/kernel/sysctl.c +@@ -2149,6 +2149,7 @@ static int do_proc_douintvec_conv(bool * + *valp = *lvalp; + } else { + unsigned int val = *valp; ++ *negp = false; + *lvalp = (unsigned long)val; + } + return 0; diff --git a/queue-4.9/sysctl-report-einval-if-value-is-larger-than-uint_max-for-proc_douintvec.patch b/queue-4.9/sysctl-report-einval-if-value-is-larger-than-uint_max-for-proc_douintvec.patch new file mode 100644 index 00000000000..ab4afc8a317 --- /dev/null +++ b/queue-4.9/sysctl-report-einval-if-value-is-larger-than-uint_max-for-proc_douintvec.patch @@ -0,0 +1,40 @@ +From 425fffd886bae3d127a08fa6a17f2e31e24ed7ff Mon Sep 17 00:00:00 2001 +From: Liping Zhang +Date: Fri, 7 Apr 2017 23:51:07 +0800 +Subject: sysctl: report EINVAL if value is larger than UINT_MAX for proc_douintvec + +From: Liping Zhang + +commit 425fffd886bae3d127a08fa6a17f2e31e24ed7ff upstream. + +Currently, inputting the following command will succeed but actually the +value will be truncated: + + # echo 0x12ffffffff > /proc/sys/net/ipv4/tcp_notsent_lowat + +This is not friendly to the user, so instead, we should report error +when the value is larger than UINT_MAX. + +Fixes: e7d316a02f68 ("sysctl: handle error writing UINT_MAX to u32 fields") +Signed-off-by: Liping Zhang +Cc: Subash Abhinov Kasiviswanathan +Cc: Andrew Morton +Cc: Eric W. Biederman +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + kernel/sysctl.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/kernel/sysctl.c ++++ b/kernel/sysctl.c +@@ -2146,6 +2146,8 @@ static int do_proc_douintvec_conv(bool * + if (write) { + if (*negp) + return -EINVAL; ++ if (*lvalp > UINT_MAX) ++ return -EINVAL; + *valp = *lvalp; + } else { + unsigned int val = *valp;