From: H.J. Lu <hjl.tools@gmail.com>
Date: Wed, 5 Apr 2023 16:21:32 +0000 (-0700)
Subject: <sys/platform/x86.h>: Add LBR support
X-Git-Tag: glibc-2.38~407
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fb90dc8513f67d1cc0578452aee3459e9b9ab626;p=thirdparty%2Fglibc.git

<sys/platform/x86.h>: Add LBR support

Add architectural LBR support to <sys/platform/x86.h>.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
---

diff --git a/manual/platform.texi b/manual/platform.texi
index 2ab687cbbaf..b72518ebd8b 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -406,6 +406,9 @@ the indirect branch predictor barrier (IBPB).
 @item
 @code{LAM} -- Linear Address Masking.
 
+@item
+@code{LBR} -- Architectural LBR.
+
 @item
 @code{LM} -- Long mode.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 6d9dd6dacf3..1040c2aed4f 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -219,7 +219,7 @@ enum
   x86_cpu_TSXLDTRK		= x86_cpu_index_7_edx + 16,
   x86_cpu_INDEX_7_EDX_17	= x86_cpu_index_7_edx + 17,
   x86_cpu_PCONFIG		= x86_cpu_index_7_edx + 18,
-  x86_cpu_INDEX_7_EDX_19	= x86_cpu_index_7_edx + 19,
+  x86_cpu_LBR			= x86_cpu_index_7_edx + 19,
   x86_cpu_IBT			= x86_cpu_index_7_edx + 20,
   x86_cpu_INDEX_7_EDX_21	= x86_cpu_index_7_edx + 21,
   x86_cpu_AMX_BF16		= x86_cpu_index_7_edx + 22,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 8b7e70aee1d..cfc8692392f 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -166,6 +166,7 @@ do_test (void)
   CHECK_CPU_FEATURE_PRESENT (SERIALIZE);
   CHECK_CPU_FEATURE_PRESENT (HYBRID);
   CHECK_CPU_FEATURE_PRESENT (TSXLDTRK);
+  CHECK_CPU_FEATURE_PRESENT (LBR);
   CHECK_CPU_FEATURE_PRESENT (PCONFIG);
   CHECK_CPU_FEATURE_PRESENT (IBT);
   CHECK_CPU_FEATURE_PRESENT (AMX_BF16);