From: Lucas De Marchi Date: Fri, 30 Jun 2023 20:35:06 +0000 (-0700) Subject: drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround X-Git-Tag: v6.6-rc1~136^2~14^2~35 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fc311f119425002c7f9a8fcdb10fa97f62267943;p=thirdparty%2Flinux.git drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround Now that non-masked registers are already read before programming the context reads, the additional read became redudant, so remove it. Signed-off-by: Lucas De Marchi Reviewed-by: Kenneth Graunke Link: https://patchwork.freedesktop.org/patch/msgid/20230630203509.1635216-5-lucas.demarchi@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 0a9c3be4817cf..b07f84c3fa210 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -637,10 +637,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { /* Wa_1406697149 (WaDisableBankHangMode:icl) */ - wa_write(wal, - GEN8_L3CNTLREG, - intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | - GEN8_ERRDETBCTRL); + wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL); /* WaForceEnableNonCoherent:icl * This is not the same workaround as in early Gen9 platforms, where