From: Philippe Mathieu-Daudé Date: Sun, 10 Jan 2021 21:44:59 +0000 (+0100) Subject: target/mips: Remove CPU_NANOMIPS32 definition X-Git-Tag: v6.0.0-rc0~147^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fc63010e9bb9efa95221f2873edb2006a40d4b6c;p=thirdparty%2Fqemu.git target/mips: Remove CPU_NANOMIPS32 definition nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already defined as ISA_NANOMIPS32. Remove this incorrect definition and update the single CPU implementing it, the I7200. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210112210152.2072996-3-f4bug@amsat.org> --- diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index ba22ff4bcd1..9f7bac87932 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -486,8 +486,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | - ASE_MT, + .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 | + ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b7879be9e90..3704db85532 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -86,9 +86,6 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) -/* Wave Computing: "nanoMIPS" */ -#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) - #define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT) /*