From: Greg Kroah-Hartman Date: Tue, 3 Feb 2015 03:41:00 +0000 (-0800) Subject: 3.14-stable patches X-Git-Tag: v3.18.6~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=fd5e0ed9614d93ca28d794313465ae78f58152aa;p=thirdparty%2Fkernel%2Fstable-queue.git 3.14-stable patches added patches: arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch --- diff --git a/queue-3.14/arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch b/queue-3.14/arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch new file mode 100644 index 00000000000..73570637463 --- /dev/null +++ b/queue-3.14/arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch @@ -0,0 +1,53 @@ +From 6b076991dca9817e75c37e2f0db6d52611ea42fa Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Thu, 17 Jul 2014 12:17:45 +0100 +Subject: ARM: DMA: ensure that old section mappings are flushed from the TLB + +From: Russell King + +commit 6b076991dca9817e75c37e2f0db6d52611ea42fa upstream. + +When setting up the CMA region, we must ensure that the old section +mappings are flushed from the TLB before replacing them with page +tables, otherwise we can suffer from mismatched aliases if the CPU +speculatively prefetches from these mappings at an inopportune time. + +A mismatched alias can occur when the TLB contains a section mapping, +but a subsequent prefetch causes it to load a page table mapping, +resulting in the possibility of the TLB containing two matching +mappings for the same virtual address region. + +Acked-by: Will Deacon +Signed-off-by: Russell King +Cc: Hou Pengyang +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mm/dma-mapping.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/arch/arm/mm/dma-mapping.c ++++ b/arch/arm/mm/dma-mapping.c +@@ -464,12 +464,21 @@ void __init dma_contiguous_remap(void) + map.type = MT_MEMORY_DMA_READY; + + /* +- * Clear previous low-memory mapping ++ * Clear previous low-memory mapping to ensure that the ++ * TLB does not see any conflicting entries, then flush ++ * the TLB of the old entries before creating new mappings. ++ * ++ * This ensures that any speculatively loaded TLB entries ++ * (even though they may be rare) can not cause any problems, ++ * and ensures that this code is architecturally compliant. + */ + for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); + addr += PMD_SIZE) + pmd_clear(pmd_off_k(addr)); + ++ flush_tlb_kernel_range(__phys_to_virt(start), ++ __phys_to_virt(end)); ++ + iotable_init(&map, 1); + } + } diff --git a/queue-3.14/series b/queue-3.14/series index bbcaf138e38..e75576da743 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -24,3 +24,4 @@ spi-pxa2xx-clear-cur_chip-pointer-before-starting-next-message.patch regulator-core-fix-race-condition-in-regulator_put.patch drivers-net-cpsw-discard-dual-emac-default-vlan-configuration.patch drm-i915-only-fence-tiled-region-of-object.patch +arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch