From: Greg Kroah-Hartman Date: Wed, 30 Jan 2013 16:58:22 +0000 (+0100) Subject: 3.7-stable patches X-Git-Tag: v3.0.62~15 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ff4b169e8c22719de16b465952b35358fa186b06;p=thirdparty%2Fkernel%2Fstable-queue.git 3.7-stable patches added patches: iommu-intel-disable-dmar-for-g4x-integrated-gfx.patch --- diff --git a/queue-3.7/iommu-intel-disable-dmar-for-g4x-integrated-gfx.patch b/queue-3.7/iommu-intel-disable-dmar-for-g4x-integrated-gfx.patch new file mode 100644 index 00000000000..f49aca3b454 --- /dev/null +++ b/queue-3.7/iommu-intel-disable-dmar-for-g4x-integrated-gfx.patch @@ -0,0 +1,74 @@ +From 9452618e7462181ed9755236803b6719298a13ce Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Sun, 20 Jan 2013 23:50:13 +0100 +Subject: iommu/intel: disable DMAR for g4x integrated gfx + +From: Daniel Vetter + +commit 9452618e7462181ed9755236803b6719298a13ce upstream. + +DMAR support on g4x/gm45 integrated gpus seems to be totally busted. +So don't bother, but instead disable it by default to allow distros to +unconditionally enable DMAR support. + +v2: Actually wire up the right quirk entry, spotted by Adam Jackson. + +Note that according to intel marketing materials only g45 and gm45 +support DMAR/VT-d. So we have reports for all relevant gen4 pci ids by +now. Still, keep all the other gen4 ids in the quirk table in case the +marketing stuff confused me again, which would not be the first time. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=51921 +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=538163 +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=538163 +Cc: Adam Jackson +Cc: David Woodhouse +Cc: stable@vger.kernel.org +Acked-By: David Woodhouse +Tested-by: stathis +Tested-by: Mihai Moldovan +Signed-off-by: Daniel Vetter +Signed-off-by: Mihai Moldovan +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iommu/intel-iommu.c | 21 +++++++++++++++------ + 1 file changed, 15 insertions(+), 6 deletions(-) + +--- a/drivers/iommu/intel-iommu.c ++++ b/drivers/iommu/intel-iommu.c +@@ -4234,6 +4234,21 @@ static struct iommu_ops intel_iommu_ops + .pgsize_bitmap = INTEL_IOMMU_PGSIZES, + }; + ++static void __devinit quirk_iommu_g4x_gfx(struct pci_dev *dev) ++{ ++ /* G4x/GM45 integrated gfx dmar support is totally busted. */ ++ printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); ++ dmar_map_gfx = 0; ++} ++ ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); ++ + static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) + { + /* +@@ -4242,12 +4257,6 @@ static void __devinit quirk_iommu_rwbf(s + */ + printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); + rwbf_quirk = 1; +- +- /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */ +- if (dev->revision == 0x07) { +- printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); +- dmar_map_gfx = 0; +- } + } + + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); diff --git a/queue-3.7/series b/queue-3.7/series index c0f6c6cc0c8..f4bf7ea3044 100644 --- a/queue-3.7/series +++ b/queue-3.7/series @@ -50,3 +50,4 @@ edac-fix-kcalloc-argument-order.patch asoc-arizona-use-actual-rather-than-desired-bclk-when-calculating-lrclk.patch asoc-wm2200-correct-mixer-values-and-text.patch bluetooth-fix-incorrect-strncpy-in-hidp_setup_hid.patch +iommu-intel-disable-dmar-for-g4x-integrated-gfx.patch