From: vekumar Date: Fri, 5 Jun 2015 06:38:32 +0000 (+0000) Subject: 2015-06-05 Venkataramanan Kumar X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ff6e6cb626adfc378ece611b3d35c0893071c95d;p=thirdparty%2Fgcc.git 2015-06-05 Venkataramanan Kumar * config/i386/sse.md (sse3_mwait): Swap the operand constriants. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224146 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a052bd3cf9c2..5eb2f40239e6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2015-06-05 Venkataramanan Kumar + + * config/i386/sse.md (sse3_mwait): Swap the operand constriants. + 2015-06-04 DJ Delorie * config/msp430/msp430.md (movsi_s): New. Special case for diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e44ba9a6d366..4ef51d668034 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13218,10 +13218,12 @@ (set_attr "atom_sse_attr" "fence") (set_attr "memory" "unknown")]) - +;; As per AMD and Intel ISA manuals, the first operand is extensions +;; and it goes to %ecx. The second operand received is hints and it goes +;; to %eax. (define_insn "sse3_mwait" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c")] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "c") + (match_operand:SI 1 "register_operand" "a")] UNSPECV_MWAIT)] "TARGET_SSE3" ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.