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3 weeks agopinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data
Nathan Chancellor [Wed, 12 Nov 2025 18:44:30 +0000 (11:44 -0700)] 
pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data

Clang warns (or errors with CONFIG_WERROR=y / W=e):

  pinctrl/mediatek/pinctrl-airoha.c:2064:41: error: variable 'an7583_pinctrl_drive_e2_conf' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
   2064 | static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
        |                                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~

Due to a typo, an7583_pinctrl_drive_e2_conf is only used within
ARRAY_SIZE() (hence no instance of -Wunused-variable), which is
evaluated at compile time, so it will not be needed in the final object
file.

Fix the .confs assignment for AIROHA_PINCTRL_CONFS_DRIVE_E2 in
an7583_pinctrl_match_data to clear up the warning.

Closes: https://github.com/ClangBuiltLinux/linux/issues/2142
Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Acked-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3 weeks agopinctrl: airoha: fix pinctrl function mismatch issue
Chukun Pan [Sat, 15 Nov 2025 10:00:00 +0000 (18:00 +0800)] 
pinctrl: airoha: fix pinctrl function mismatch issue

The blamed commit made the following changes:

-#define PINCTRL_FUNC_DESC(id)...
- .desc = PINCTRL_PINFUNCTION(#id, ...
+#define PINCTRL_FUNC_DESC(id, table)...
+ .desc = PINCTRL_PINFUNCTION(#id, ...

- PINCTRL_FUNC_DESC(pon)...
+ PINCTRL_FUNC_DESC("pon", pon)...

It's clear that the id of funcs doesn't match the definition.
Remove redundant #string from the definition to fix this issue:
pinctrl-airoha ...: invalid function mdio in map table

Fixes: 4043b0c45f85 ("pinctrl: airoha: generalize pins/group/function/confs handling")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Acked-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
3 weeks agoMerge tag 'renesas-pinctrl-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux...
Linus Walleij [Tue, 18 Nov 2025 23:00:58 +0000 (00:00 +0100)] 
Merge tag 'renesas-pinctrl-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v6.19 (take two)

  - Remove removed signals on R-Car V4H and V4M,
  - Refactor OEN register PWPR handling on RZ/G2L.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: renesas: rzg2l: Refactor OEN register PWPR handling
John Madieu [Thu, 6 Nov 2025 08:07:58 +0000 (09:07 +0100)] 
pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling

Extract the OEN register write with PWPR protection logic into a helper
function to eliminate code duplication between rzg2l_write_oen() and
rzg2l_pinctrl_resume_noirq().

Introduce rzg2l_oen_write_with_pwpr() helper that encapsulates the
PWPR unlock, OEN register write, and PWPR lock sequence. This helper
must be called with pctrl->lock already held by the caller.

Reported-by: Pavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/cip-dev/OS9PR01MB16368C765305362F5F4132759FFC4A@OS9PR01MB16368.jpnprd01.prod.outlook.com/T/#u
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251106080758.36645-1-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 weeks agopinctrl: airoha: convert comma to semicolon
Chen Ni [Tue, 11 Nov 2025 06:29:44 +0000 (14:29 +0800)] 
pinctrl: airoha: convert comma to semicolon

Replace comma between expressions with semicolons.

Using a ',' in place of a ';' can have unintended side effects.
Although that is not the case here, it is seems best to use ';'
unless ',' is intended.

Found by inspection.
No functional change intended.
Compile tested only.

Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: airoha: add support for Airoha AN7583 PINs
Christian Marangi [Thu, 6 Nov 2025 23:57:08 +0000 (00:57 +0100)] 
pinctrl: airoha: add support for Airoha AN7583 PINs

Add all the required entry to add suppot for Airoha AN7583 PINs.

Where possible the same function group are used from Airoha EN7581 to
reduce code duplication.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agodt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
Christian Marangi [Thu, 6 Nov 2025 23:57:07 +0000 (00:57 +0100)] 
dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller

Document Airoha AN7583 Pin Controller based on Airoha EN7581 with some
minor difference on some function group (PCM and LED gpio).

To not bloat the EN7581 schema with massive if condition, use a
dedicated YAML schema for Airoha AN7583.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: airoha: convert PWM GPIO to macro
Christian Marangi [Thu, 6 Nov 2025 23:57:06 +0000 (00:57 +0100)] 
pinctrl: airoha: convert PWM GPIO to macro

The PWM GPIO struct definition follow the same pattern for every GPIO
pin hence it can be converted to a macro.

Create 2 macro one for normal mux and one for ext mux and convert all
the entry to these new macro to reduce code size.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: airoha: convert PHY LED GPIO to macro
Christian Marangi [Thu, 6 Nov 2025 23:57:05 +0000 (00:57 +0100)] 
pinctrl: airoha: convert PHY LED GPIO to macro

PHY LED GPIO pinctrl struct definition is very similar across the
different 4 PHY and 2 LED and it can be generelized to a macro.

To reduce code size, convert them to a common macro.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: airoha: generalize pins/group/function/confs handling
Christian Marangi [Thu, 6 Nov 2025 23:57:04 +0000 (00:57 +0100)] 
pinctrl: airoha: generalize pins/group/function/confs handling

In preparation for support of Airoha AN7583, generalize
pins/group/function/confs handling and move them in match_data.
Inner function will base the values on the pinctrl priv struct instead of
relying on hardcoded struct.

This permits to use different PIN data while keeping the same logic.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agodt-bindings: pinctrl: mt7988: allow gpio-hogs
Frank Wunderlich [Mon, 27 Oct 2025 13:28:11 +0000 (14:28 +0100)] 
dt-bindings: pinctrl: mt7988: allow gpio-hogs

Allow gpio-hogs in pinctrl node for switching pcie on Bananapi R4 Pro.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogiocchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: stm32: handle semaphore acquisition when handling pinctrl/pinmux
Gatien Chevallier [Wed, 5 Nov 2025 10:50:22 +0000 (11:50 +0100)] 
pinctrl: stm32: handle semaphore acquisition when handling pinctrl/pinmux

When a GPIO RIF configuration is in semaphore mode, and the semaphore
hasn't been taken before configuring the GPIO, the write operations
silently fail.

To avoid a silent fail when applying a pinctrl, if the pins that are
being configured are in semaphore mode, take the semaphore. Note that
there is no proper release of the RIF semaphore yet for pinctrl.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: rockchip: Add rk3506 pinctrl support
Ye Zhang [Tue, 4 Nov 2025 02:12:22 +0000 (10:12 +0800)] 
pinctrl: rockchip: Add rk3506 pinctrl support

Add support for the 5 rk3506 GPIO banks.

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agodt-bindings: pinctrl: Add rk3506 pinctrl support
Ye Zhang [Tue, 4 Nov 2025 02:12:21 +0000 (10:12 +0800)] 
dt-bindings: pinctrl: Add rk3506 pinctrl support

Add the compatible string for the rk3506 SoC.

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agoMerge tag 'samsung-pinctrl-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git...
Linus Walleij [Mon, 10 Nov 2025 20:55:16 +0000 (21:55 +0100)] 
Merge tag 'samsung-pinctrl-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v6.19

Add pin controller support for Samsung Exynos8890 and Axis ARTPEC-9
SoCs.  The latter is a newer design of Artpec SoCs made/designed by
Samsung, thus it shares most of the core blocks with Samsung Exynos,
including the pinctrl.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agodt-bindings: pinctrl: Convert sprd,sc9860-pinctrl to DT schema
Rob Herring (Arm) [Mon, 27 Oct 2025 21:26:41 +0000 (16:26 -0500)] 
dt-bindings: pinctrl: Convert sprd,sc9860-pinctrl to DT schema

Convert the sprd,sc9860-pinctrl binding to DT schema format. What's
valid for the the sleep mode child nodes wasn't well defined. The schema
is based on the example (as there's no .dts with pin states) and the
driver's register definitions.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
4 weeks agopinctrl: renesas: r8a779h0: Remove STPWT_EXTFXR
Geert Uytterhoeven [Tue, 4 Nov 2025 16:59:47 +0000 (17:59 +0100)] 
pinctrl: renesas: r8a779h0: Remove STPWT_EXTFXR

Rev.0.81 of the R-Car V4M Series Hardware User’s Manual removed the
"STPWT_EXTFXR" signal from the pin control register tables.  As this is
further unused in the pin control driver, it can be removed safely.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/f849fa3b9b516e9dd04b45462b69f52225259480.1762274384.git.geert+renesas@glider.be
4 weeks agopinctrl: renesas: r8a779h0: Remove CC5_OSCOUT
Huy Bui [Tue, 4 Nov 2025 16:59:46 +0000 (17:59 +0100)] 
pinctrl: renesas: r8a779h0: Remove CC5_OSCOUT

Rev.0.71 of the R-Car V4M Series Hardware User’s Manual removed the
"CC5_OSCOUT" signal from the pin control register tables.  As this is
further unused in the pin control driver, it can be removed safely.

Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/895bb560467309706931d14aeea0e063ad0e86eb.1762274384.git.geert+renesas@glider.be
4 weeks agopinctrl: renesas: r8a779g0: Remove STPWT_EXTFXR
Huy Bui [Tue, 4 Nov 2025 16:59:45 +0000 (17:59 +0100)] 
pinctrl: renesas: r8a779g0: Remove STPWT_EXTFXR

Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the
"STPWT_EXTFXR" signal from the pin control register tables.  As this is
further unused in the pin control driver, it can be removed safely.

Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/f6cfdbbc024d85e87583a1d57ea01582632f1216.1762274384.git.geert+renesas@glider.be
4 weeks agopinctrl: renesas: r8a779g0: Remove CC5_OSCOUT
Huy Bui [Tue, 4 Nov 2025 16:59:44 +0000 (17:59 +0100)] 
pinctrl: renesas: r8a779g0: Remove CC5_OSCOUT

Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the
"CC5_OSCOUT" signal from the pin control register tables.  As this is
further unused in the pin control driver, it can be removed safely.

Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/77f9efe5388f2801ace945b7793d4823618eeec8.1762274384.git.geert+renesas@glider.be
4 weeks agopinctrl: renesas: r8a779g0: Remove AVB[01]_MII
Thanh Quan [Tue, 4 Nov 2025 16:59:43 +0000 (17:59 +0100)] 
pinctrl: renesas: r8a779g0: Remove AVB[01]_MII

Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the
"AVB[01]_MII_*" signals from the pin control register tables.  As these
are further unused in the pin control driver, they can be removed
safely.

Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/58662f50136280532bcc8bbe94741d82425bd118.1762274384.git.geert+renesas@glider.be
4 weeks agoMerge tag 'renesas-pinctrl-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux...
Linus Walleij [Sun, 9 Nov 2025 22:55:18 +0000 (23:55 +0100)] 
Merge tag 'renesas-pinctrl-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v6.19

  - Fix interrupt configuration and port mode after resume on RZ/G2L
    family SoCs,
  - Miscellaneous fixes and improvements.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
5 weeks agopinctrl: cix: sky1: Provide pin control dummy states
Linus Walleij [Tue, 4 Nov 2025 13:01:03 +0000 (14:01 +0100)] 
pinctrl: cix: sky1: Provide pin control dummy states

This exports and calls the pinctrl_provide_dummies() function from
the CIX SKY1 driver.

The reasons are explained in a comment in the commit, in essence the
two pin controllers need to go through explicit state transitions
default->sleep->default despite they only handle one single state
each.

Reviewed-by: Hans Zhang <hans.zhang@cixtech.com>
Reviewed-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: mpfs-iomux0: fix compile-time constant warning for LLVM prior to 17
Conor Dooley [Wed, 29 Oct 2025 15:29:35 +0000 (15:29 +0000)] 
pinctrl: mpfs-iomux0: fix compile-time constant warning for LLVM prior to 17

With LLVM prior to 17.0.0:

drivers/pinctrl/pinctrl-mpfs-iomux0.c:89:2: error: initializer element is not a compile-time constant
        MPFS_IOMUX0_GROUP(spi0),
        ^~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-mpfs-iomux0.c:79:10: note: expanded from macro 'MPFS_IOMUX0_GROUP'
        .mask = BIT(mpfs_iomux0_##_name##_pins[0]),     \
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/vdso/bits.h:7:19: note: expanded from macro 'BIT'
\#define BIT(nr)                 (UL(1) << (nr))
                                ^~~~~~~~~~~~~~~

This is a constant, but LLVM prior to a change from Nick to match the
gcc behaviour did not allow this. The macro isn't really all that much
of an idiot-proofing, just change it to the same sort that's in the
gpio2 driver, where a second argument provides the mask/setting.

Reported-by: Nathan Chancellor <nathan@kernel.org>
Link: https://github.com/ClangBuiltLinux/linux/issues/2140
Fixes: 46397274da22 ("pinctrl: add polarfire soc iomux0 pinmux driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: stm32: fix hwspinlock resource leak in probe function
Haotian Zhang [Wed, 29 Oct 2025 01:42:52 +0000 (09:42 +0800)] 
pinctrl: stm32: fix hwspinlock resource leak in probe function

In stm32_pctl_probe(), hwspin_lock_request_specific() is called to
request a hwspinlock, but the acquired lock is not freed on multiple
error paths after this call. This causes resource leakage when the
function fails to initialize properly.

Use devm_hwspin_lock_request_specific() instead of
hwspin_lock_request_specific() to automatically manage the hwspinlock
resource lifecycle.

Fixes: 97cfb6cd34f2 ("pinctrl: stm32: protect configuration registers with a hwspinlock")
Signed-off-by: Haotian Zhang <vulab@iscas.ac.cn>
Reviewed-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: mcp23s08: init reg_defaults from HW at probe and switch cache type
Maksim Kiselev [Mon, 27 Oct 2025 10:46:26 +0000 (13:46 +0300)] 
pinctrl: mcp23s08: init reg_defaults from HW at probe and switch cache type

The probe function does not guarantee that chip registers are in their
default state. Thus using reg_defaults for regmap is incorrect.

For example, the chip may have already been configured by the bootloader
before the Linux driver loads, or the mcp might not have a reset at all
and not reset a state between reboots.

In such cases, using reg_defaults leads to the cache values diverging
from the actual registers values in the chip.

Previous attempts to fix consequences of this issue were made in
'commit 3ede3f8b4b4b ("pinctrl: mcp23s08: Reset all pins to input at
probe")', but this is insufficient. The OLAT register reset is also
required. And there's still potential for new issues arising due to cache
desynchronization of other registers.

Therefore, remove reg_defaults and provide num_reg_defaults_raw. In that
case the cache defaults being initialized from hardware.

Also switch cache type to REGCACHE_MAPLE, which is aware of (in)valid
cache entries.

And remove the force reset all pins to input at probe as it is no longer
required.

Link: https://lore.kernel.org/all/20251009132651.649099-2-bigunclemax@gmail.com/
Suggested-by: Mike Looijmans <mike.looijmans@topic.nl>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl-scmi: remove unused struct members
Dan Carpenter [Mon, 27 Oct 2025 15:18:20 +0000 (18:18 +0300)] 
pinctrl-scmi: remove unused struct members

The ->pins and ->nr_pins members are not used so delete them.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agodt-bindings: pinctrl: stm32: Support I/O synchronization parameters
Antonio Borneo [Thu, 23 Oct 2025 13:26:59 +0000 (15:26 +0200)] 
dt-bindings: pinctrl: stm32: Support I/O synchronization parameters

Document the support of the I/O synchronization parameters:
- skew-delay-input-ps;
- skew-delay-output-ps;
- st,io-sync.

Forbid 'skew-delay-input-ps' and 'skew-delay-output-ps' to be both
present on the same pin.
Allow the new properties only with compatibles that support them.
Add an example that uses the new properties.

Co-developed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agodt-bindings: pinctrl: stm32: Use properties from pincfg-node.yaml
Antonio Borneo [Thu, 23 Oct 2025 13:26:58 +0000 (15:26 +0200)] 
dt-bindings: pinctrl: stm32: Use properties from pincfg-node.yaml

Don't re-declare the standard pincfg properties; take them from
the default schema.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: stm32: Support I/O synchronization parameters
Antonio Borneo [Thu, 23 Oct 2025 13:26:57 +0000 (15:26 +0200)] 
pinctrl: stm32: Support I/O synchronization parameters

Devices in the stm32mp2xx family include an I/O synchronization
block on each pin that is used to fine tune and improve the I/O
timing margins of high speed synchronous interfaces.
It can be configured to provide independently for each pin:
- skew rate on input direction or latch delay on output direction;
- inversion of clock signals or re-sampling of data signals.

Add support for the generic properties:
- skew-delay-input-ps;
- skew-delay-output-ps.

Add support for the property 'st,io-sync' to configure clock
inversion or data re-sampling mode.

Show the new parameters on debugfs pinconf-pins.

Enable it for the stm32mp257 pinctrl driver.

Co-developed-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Co-developed-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: stm32: Avoid keeping a bool value in a u32 variable
Antonio Borneo [Thu, 23 Oct 2025 13:26:56 +0000 (15:26 +0200)] 
pinctrl: stm32: Avoid keeping a bool value in a u32 variable

Change type of variable to avoid keeping the bool return value in
a variable of u32 type.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: stm32: Drop useless spinlock save and restore
Antonio Borneo [Thu, 23 Oct 2025 13:26:55 +0000 (15:26 +0200)] 
pinctrl: stm32: Drop useless spinlock save and restore

There is no need to acquire a spinlock to only read a register for
debugfs reporting.
Drop such useless spinlock save and restore.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: stm32: Simplify handling of backup pin status
Antonio Borneo [Thu, 23 Oct 2025 13:26:54 +0000 (15:26 +0200)] 
pinctrl: stm32: Simplify handling of backup pin status

Use C bit-field to keep the backup of the pin status, instead of
explicitly handling the bit-field through shift and mask of a u32
container.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: stm32: Rework stm32_pconf_parse_conf()
Antonio Borneo [Thu, 23 Oct 2025 13:26:53 +0000 (15:26 +0200)] 
pinctrl: stm32: Rework stm32_pconf_parse_conf()

Reduce the number of parameters of the function by moving inside
the function the decoding of the field 'config'.

While there:
- change the type of 'param' to 'unsigned int' to handle the extra
  values not in 'enum pin_config_param';
- change the type of 'arg' to 'u32' to avoid additional conversions
  and align to 'u32' the corresponding param of __stm32_gpio_set().

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agodt-bindings: pincfg-node: Add properties 'skew-delay-{in,out}put-ps'
Antonio Borneo [Thu, 23 Oct 2025 13:26:52 +0000 (15:26 +0200)] 
dt-bindings: pincfg-node: Add properties 'skew-delay-{in,out}put-ps'

Add the properties 'skew-delay-input-ps' and 'skew-delay-output-ps'
to specify independent skew delay value for the two pin's directions.
Make the new properties unavailable when the existing property
'skew-delay' is selected.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: pinconf-generic: Add properties 'skew-delay-{in,out}put-ps'
Antonio Borneo [Thu, 23 Oct 2025 13:26:51 +0000 (15:26 +0200)] 
pinctrl: pinconf-generic: Add properties 'skew-delay-{in,out}put-ps'

Add the properties 'skew-delay-input-ps' and 'skew-delay-output-ps'
to the generic parameters used for parsing DT files. This allows to
specify the independent skew delay value for the two directions.
This enables drivers that use the generic pin configuration to get
the value passed through these new properties.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: pinconf-generic: Handle string values for generic properties
Antonio Borneo [Thu, 23 Oct 2025 13:26:50 +0000 (15:26 +0200)] 
pinctrl: pinconf-generic: Handle string values for generic properties

Allow a generic pinconf property to specify its argument as one of
the strings in a match list.
Convert the matching string to an integer value using the index in
the list, then keep using this value in the generic pinconf code.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: pinconf-generic: Fix minor typos in comments
Antonio Borneo [Thu, 23 Oct 2025 13:26:49 +0000 (15:26 +0200)] 
pinctrl: pinconf-generic: Fix minor typos in comments

s/specyfying/specifying/
s/propertity/property/

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: cix: Add pin-controller support for sky1
Gary Yang [Tue, 21 Oct 2025 07:04:09 +0000 (15:04 +0800)] 
pinctrl: cix: Add pin-controller support for sky1

There are two pin-controllers on Cix Sky1 platform.
one is used under S0 state, the other is used under S0 and S5 state.

Signed-off-by: Gary Yang <gary.yang@cixtech.com>
[Dropped pinctrl_provide_dummies()]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agodt-bindings: pinctrl: Add cix,sky1-pinctrl
Gary Yang [Tue, 21 Oct 2025 07:04:08 +0000 (15:04 +0800)] 
dt-bindings: pinctrl: Add cix,sky1-pinctrl

The pin-controller is used to control the Soc pins.
There are two pin-controllers on Cix Sky1 platform.
One is used under S0 state, the other is used under
S0 and S5 state.

Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
6 weeks agopinctrl: renesas: rzg2l: Remove useless wrappers
Cosmin Tanislav [Wed, 22 Oct 2025 07:40:58 +0000 (10:40 +0300)] 
pinctrl: renesas: rzg2l: Remove useless wrappers

rzg2l_gpio_irq_set_type() and rzg2l_gpio_irqc_eoi() only call the
equivalent parent functions, replace their usage with the parent
functions and remove them.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251022074100.1994447-1-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
7 weeks agoMAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry
Conor Dooley [Thu, 23 Oct 2025 17:15:01 +0000 (18:15 +0100)] 
MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry

Add the new gpio2 and iomux0 drivers and bindings to the existing entry
for Microchip RISC-V devices.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agopinctrl: add polarfire soc iomux0 pinmux driver
Conor Dooley [Thu, 23 Oct 2025 17:15:00 +0000 (18:15 +0100)] 
pinctrl: add polarfire soc iomux0 pinmux driver

On Polarfire SoC, iomux0 is responsible for routing functions to either
Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
can either interface with custom RTL or be routed to the FPGA fabric's
IOs. Add a driver for it.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: pinctrl: document polarfire soc iomux0 pinmux
Conor Dooley [Thu, 23 Oct 2025 17:14:59 +0000 (18:14 +0100)] 
dt-bindings: pinctrl: document polarfire soc iomux0 pinmux

On Polarfire SoC, iomux0 is responsible for routing functions to either
Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
can either interface with custom RTL or be routed to the FPGA fabric's
IOs. Document it.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agopinctrl: add pic64gx "gpio2" pinmux driver
Conor Dooley [Thu, 23 Oct 2025 17:14:58 +0000 (18:14 +0100)] 
pinctrl: add pic64gx "gpio2" pinmux driver

The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The
documentation for the SoC provides no name for this device, but it is
used to swap pins between either GPIO controller #2 or select other
functions, hence the "gpio2" name. Add a driver for it.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: pinctrl: document pic64gx "gpio2" pinmux
Conor Dooley [Thu, 23 Oct 2025 17:14:57 +0000 (18:14 +0100)] 
dt-bindings: pinctrl: document pic64gx "gpio2" pinmux

The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The
documentation for the SoC provides no name for this device, but it is
used to swap pins between either GPIO controller #2 or select other
functions, hence the "gpio2" name. Currently there is no documentation
about what each bit actually does that is publicly available, nor (I
believe) what pins are affected. That info is as follows:

pin     role (1/0)
---     ----------
E14 MAC_0_MDC/GPIO_2_0
E15 MAC_0_MDIO/GPIO_2_1
F16 MAC_1_MDC/GPIO_2_2
F17 MAC_1_MDIO/GPIO_2_3
D19 SPI_0_CLK/GPIO_2_4
B18 SPI_0_SS0/GPIO_2_5
B10 CAN_0_RXBUS/GPIO_2_6
C14 PCIE_PERST_2#/GPIO_2_7
E18 PCIE_WAKE#/GPIO_2_8
D18 PCIE_PERST_1#/GPIO_2_9
E19 SPI_0_DO/GPIO_2_10
C7 SPI_0_DI/GPIO_2_11
D6 QSPI_SS0/GPIO_2_12
D7 QSPI_CLK (B)/GPIO_2_13
C9 QSPI_DATA0/GPIO_2_14
C10 QSPI_DATA1/GPIO_2_15
A5 QSPI_DATA2/GPIO_2_16
A6 QSPI_DATA3/GPIO_2_17
D8 MMUART_3_RXD/GPIO_2_18
D9 MMUART_3_TXD/GPIO_2_19
B8 MMUART_4_RXD/GPIO_2_20
A8 MMUART_4_TXD/GPIO_2_21
C12 CAN_1_TXBUS/GPIO_2_22
B12 CAN_1_RXBUS/GPIO_2_23
A11 CAN_0_TX_EBL_N/GPIO_2_24
A10 CAN_1_TX_EBL_N/GPIO_2_25
D11 MMUART_2_RXD/GPIO_2_26
C11 MMUART_2_TXD/GPIO_2_27
B9 CAN_0_TXBUS/GPIO_2_28

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agoMerge tag 'mpfs-pinctrl-binding-base' of https://git.kernel.org/pub/scm/linux/kernel...
Linus Walleij [Fri, 24 Oct 2025 09:07:47 +0000 (11:07 +0200)] 
Merge tag 'mpfs-pinctrl-binding-base' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into devel

mpfs pinctrl binding base

The pinctrl binding patch for iomux0 mpfs adds a ref to itself to the
syscon/mfd mss-top-sysreg binding, and therefore needs that file to
exist.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agopinctrl: renesas: rza1: Make mux_conf const in rza1_pin_mux_single()
Geert Uytterhoeven [Tue, 21 Oct 2025 08:06:05 +0000 (10:06 +0200)] 
pinctrl: renesas: rza1: Make mux_conf const in rza1_pin_mux_single()

The rza1_mux_conf object pointed to by the mux_conf parameter of
rza1_pin_mux_single() is never modified.  Make it const.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://patch.msgid.link/168e06bc57081aa3c42ff9aa2740a0a108df7d34.1761033950.git.geert+renesas@glider.be
7 weeks agodt-bindings: pinctrl: toshiba,visconti: Drop redundant functions type
Krzysztof Kozlowski [Wed, 22 Oct 2025 13:34:27 +0000 (15:34 +0200)] 
dt-bindings: pinctrl: toshiba,visconti: Drop redundant functions type

Referenced pinmux-node.yaml schema already defines type for "functions"
so $ref is redundant.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agopinctrl: pinmux: Add missing .function_is_gpio kerneldoc
Linus Walleij [Wed, 22 Oct 2025 13:23:42 +0000 (15:23 +0200)] 
pinctrl: pinmux: Add missing .function_is_gpio kerneldoc

This callback was undocumented, add the docs.

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: pinctrl: Convert bitmain,bm1880-pinctrl to DT schema
Rob Herring (Arm) [Mon, 13 Oct 2025 19:12:33 +0000 (14:12 -0500)] 
dt-bindings: pinctrl: Convert bitmain,bm1880-pinctrl to DT schema

Convert the bitmain,bm1880-pinctrl binding to DT schema format. It's a
straight-forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: pinctrl: Convert brcm,ns2-pinmux to DT schema
Rob Herring (Arm) [Mon, 13 Oct 2025 19:12:25 +0000 (14:12 -0500)] 
dt-bindings: pinctrl: Convert brcm,ns2-pinmux to DT schema

Convert the brcm,ns2-pinmux binding to DT schema format. It's a
straight-forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: pinctrl: Convert actions,s900-pinctrl to DT schema
Rob Herring (Arm) [Mon, 13 Oct 2025 19:12:16 +0000 (14:12 -0500)] 
dt-bindings: pinctrl: Convert actions,s900-pinctrl to DT schema

Convert the actions,s900-pinctrl binding to DT schema format. It's a
straight-forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: pinctrl: Convert actions,s700-pinctrl to DT schema
Rob Herring (Arm) [Mon, 13 Oct 2025 19:12:05 +0000 (14:12 -0500)] 
dt-bindings: pinctrl: Convert actions,s700-pinctrl to DT schema

Convert the actions,s700-pinctrl binding to DT schema format. It's a
straight-forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
7 weeks agodt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC
Conor Dooley [Mon, 13 Oct 2025 17:45:33 +0000 (18:45 +0100)] 
dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC

"mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller
and more. At this point, only the reset controller child is described as
that's all that is described by the existing bindings.
The clock controller already has a dedicated node, and will retain it as
there are other clock regions, so like the mailbox, a compatible-based
lookup of the syscon is sufficient to keep the clock driver working as
before, so no child is needed. There's also an interrupt multiplexing
service provided by this syscon, for which there is work in progress at
[1].

Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a4fefe@wendy/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2 months agopinctrl: tegra20: register csus_mux clock
Svyatoslav Ryhel [Wed, 8 Oct 2025 07:30:23 +0000 (10:30 +0300)] 
pinctrl: tegra20: register csus_mux clock

Add csus_mux for further use as the csus clock parent, similar to how the
cdev1 and cdev2 muxes are utilized. Additionally, constify the cdev parent
name lists to resolve checkpatch warnings.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: renesas: Remove unneeded semicolons
Geert Uytterhoeven [Wed, 24 Sep 2025 12:47:52 +0000 (14:47 +0200)] 
pinctrl: renesas: Remove unneeded semicolons

Semicolons after end of function braces are not needed, remove them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/99db8c1bfb64980b54a4b5c4988c7935609133e1.1758718027.git.geert+renesas@glider.be
2 months agopinctrl: renesas: rzg2l: Remove extra semicolons
Cosmin Tanislav [Tue, 23 Sep 2025 17:49:50 +0000 (20:49 +0300)] 
pinctrl: renesas: rzg2l: Remove extra semicolons

Semicolons after end of function braces are unnecessary, remove them.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250923174951.1136259-1-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agopinctrl: renesas: rzg2l: Fix PMC restore
Biju Das [Sun, 21 Sep 2025 11:15:52 +0000 (12:15 +0100)] 
pinctrl: renesas: rzg2l: Fix PMC restore

PMC restore needs unlocking the register using the PWPR register.

Fixes: ede014cd1ea6422d ("pinctrl: renesas: rzg2l: Add function pointer for PMC register write")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250921111557.103069-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agopinctrl: renesas: Drop duplicate newlines
Marek Vasut [Thu, 18 Sep 2025 20:04:01 +0000 (22:04 +0200)] 
pinctrl: renesas: Drop duplicate newlines

Remove duplicate newlines.  No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250918200409.37284-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agopinctrl: renesas: rzg2l: Drop unnecessary pin configurations
Biju Das [Tue, 9 Sep 2025 10:42:44 +0000 (11:42 +0100)] 
pinctrl: renesas: rzg2l: Drop unnecessary pin configurations

There is no need to reconfigure a pin if the pin's configuration
values are the same as the reset values.  E.g. the PS0 pin configuration
for the NMI function is PMC = 1 and PFC = 0, which is the same as the
reset values.  Currently the code is first setting it to GPIO HI-Z state
and then again reconfiguring to the NMI function, leading to spurious
IRQs.  Fix this by dropping unnecessary pin configuration from the
driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250909104247.3309-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agopinctrl: renesas: rzg2l: Fix ISEL restore on resume
Claudiu Beznea [Fri, 12 Sep 2025 09:53:08 +0000 (12:53 +0300)] 
pinctrl: renesas: rzg2l: Fix ISEL restore on resume

Commit 1d2da79708cb ("pinctrl: renesas: rzg2l: Avoid configuring ISEL in
gpio_irq_{en,dis}able*()") dropped the configuration of ISEL from
struct irq_chip::{irq_enable, irq_disable} APIs and moved it to
struct gpio_chip::irq::{child_to_parent_hwirq,
child_irq_domain_ops::free} APIs to fix spurious IRQs.

After commit 1d2da79708cb ("pinctrl: renesas: rzg2l: Avoid configuring ISEL
in gpio_irq_{en,dis}able*()"), ISEL was no longer configured properly on
resume. This is because the pinctrl resume code used
struct irq_chip::irq_enable  (called from rzg2l_gpio_irq_restore()) to
reconfigure the wakeup interrupts. Some drivers (e.g. Ethernet) may also
reconfigure non-wakeup interrupts on resume through their own code,
eventually calling struct irq_chip::irq_enable.

Fix this by adding ISEL configuration back into the
struct irq_chip::irq_enable API and on resume path for wakeup interrupts.

As struct irq_chip::irq_enable needs now to lock to update the ISEL,
convert the struct rzg2l_pinctrl::lock to a raw spinlock and replace the
locking API calls with the raw variants. Otherwise the lockdep reports
invalid wait context when probing the adv7511 module on RZ/G2L:

 [ BUG: Invalid wait context ]
 6.17.0-rc5-next-20250911-00001-gfcfac22533c9 #18 Not tainted
 -----------------------------
 (udev-worker)/165 is trying to lock:
 ffff00000e3664a8 (&pctrl->lock){....}-{3:3}, at: rzg2l_gpio_irq_enable+0x38/0x78
 other info that might help us debug this:
 context-{5:5}
 3 locks held by (udev-worker)/165:
 #0: ffff00000e890108 (&dev->mutex){....}-{4:4}, at: __driver_attach+0x90/0x1ac
 #1: ffff000011c07240 (request_class){+.+.}-{4:4}, at: __setup_irq+0xb4/0x6dc
 #2: ffff000011c070c8 (lock_class){....}-{2:2}, at: __setup_irq+0xdc/0x6dc
 stack backtrace:
 CPU: 1 UID: 0 PID: 165 Comm: (udev-worker) Not tainted 6.17.0-rc5-next-20250911-00001-gfcfac22533c9 #18 PREEMPT
 Hardware name: Renesas SMARC EVK based on r9a07g044l2 (DT)
 Call trace:
 show_stack+0x18/0x24 (C)
 dump_stack_lvl+0x90/0xd0
 dump_stack+0x18/0x24
 __lock_acquire+0xa14/0x20b4
 lock_acquire+0x1c8/0x354
 _raw_spin_lock_irqsave+0x60/0x88
 rzg2l_gpio_irq_enable+0x38/0x78
 irq_enable+0x40/0x8c
 __irq_startup+0x78/0xa4
 irq_startup+0x108/0x16c
 __setup_irq+0x3c0/0x6dc
 request_threaded_irq+0xec/0x1ac
 devm_request_threaded_irq+0x80/0x134
 adv7511_probe+0x928/0x9a4 [adv7511]
 i2c_device_probe+0x22c/0x3dc
 really_probe+0xbc/0x2a0
 __driver_probe_device+0x78/0x12c
 driver_probe_device+0x40/0x164
 __driver_attach+0x9c/0x1ac
 bus_for_each_dev+0x74/0xd0
 driver_attach+0x24/0x30
 bus_add_driver+0xe4/0x208
 driver_register+0x60/0x128
 i2c_register_driver+0x48/0xd0
 adv7511_init+0x5c/0x1000 [adv7511]
 do_one_initcall+0x64/0x30c
 do_init_module+0x58/0x23c
 load_module+0x1bcc/0x1d40
 init_module_from_file+0x88/0xc4
 idempotent_init_module+0x188/0x27c
 __arm64_sys_finit_module+0x68/0xac
 invoke_syscall+0x48/0x110
 el0_svc_common.constprop.0+0xc0/0xe0
 do_el0_svc+0x1c/0x28
 el0_svc+0x4c/0x160
 el0t_64_sync_handler+0xa0/0xe4
 el0t_64_sync+0x198/0x19c

Having ISEL configuration back into the struct irq_chip::irq_enable API
should be safe with respect to spurious IRQs, as in the probe case IRQs
are enabled anyway in struct gpio_chip::irq::child_to_parent_hwirq. No
spurious IRQs were detected on suspend/resume, boot, ethernet link
insert/remove tests (executed on RZ/G3S). Boot, ethernet link
insert/remove tests were also executed successfully on RZ/G2L.

Fixes: 1d2da79708cb ("pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*(")
Cc: stable@vger.kernel.org
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250912095308.3603704-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2 months agopinctrl: Demote subsystem banner message
Linus Walleij [Tue, 7 Oct 2025 13:18:50 +0000 (15:18 +0200)] 
pinctrl: Demote subsystem banner message

There is no reason to print any "hello world" from pin control
unless (maybe) if we are debugging.

Drop the banner.

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add QCM2290 compatible
Alexey Klimov [Tue, 7 Oct 2025 02:03:29 +0000 (03:03 +0100)] 
dt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add QCM2290 compatible

Add a compatible for the LPASS LPI pin controller on QCM2290. It seems
to be compatible with sm6115 LPASS pinctrl.

Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Srinivas Kandagatla <srini@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: qcom: add the tlmm driver for Kaanapali platforms
Jingyi Wang [Wed, 24 Sep 2025 23:16:04 +0000 (16:16 -0700)] 
pinctrl: qcom: add the tlmm driver for Kaanapali platforms

Add support for Kaanapali TLMM configuration and control via the pinctrl
framework.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: describe Kaanapali TLMM
Jingyi Wang [Wed, 24 Sep 2025 23:16:03 +0000 (16:16 -0700)] 
dt-bindings: pinctrl: describe Kaanapali TLMM

The Top Level Mode Multiplexer (TLMM) in the Kaanapali SoC provide GPIO and
pinctrl functionality for UFS, SDC and 217 GPIO pins.

Add a DeviceTree binding to describe the Kaanapali TLMM block.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema
Rob Herring (Arm) [Thu, 25 Sep 2025 22:18:50 +0000 (17:18 -0500)] 
dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema

Convert the marvell,armada3710-(sb|nb)-pinctrl binding to DT schema
format. The binding includes the "marvell,armada-3700-xtal-clock"
subnode which is simple enough to include here.

Mark interrupt-controller/#interrupt-cells as required as the users have
them and the h/w is either capable of interrupts or not.

As this syscon has 2 register ranges, syscon-common.yaml needs to be
updated to drop the restriction of 1 register entry.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: Convert Marvell Berlin pinctrl to DT schema
Rob Herring (Arm) [Wed, 24 Sep 2025 22:31:59 +0000 (17:31 -0500)] 
dt-bindings: pinctrl: Convert Marvell Berlin pinctrl to DT schema

Convert the Marvell/Synaptics Berlin pinctrl binding to DT schema
format. The "reg" property was not documented for the newer SoCs.
Otherwise, it's a straight-forward conversion.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: qcom: spmi-gpio: add support for {LV_VIN2, MV_VIN3}_CLK subtypes
Subbaraman Narayanamurthy [Wed, 24 Sep 2025 17:01:04 +0000 (22:31 +0530)] 
pinctrl: qcom: spmi-gpio: add support for {LV_VIN2, MV_VIN3}_CLK subtypes

Add support for SPMI PMIC GPIO subtypes GPIO_LV_VIN2_CLK and
GPIO_MV_VIN3_CLK.

Signed-off-by: Subbaraman Narayanamurthy <subbaraman.narayanamurthy@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: qcom: spmi-gpio: Add PMCX0102, PMK8850 & PMH01XX PMICs support
Anjelique Melendez [Wed, 24 Sep 2025 17:01:03 +0000 (22:31 +0530)] 
pinctrl: qcom: spmi-gpio: Add PMCX0102, PMK8850 & PMH01XX PMICs support

Add support for PMCX0102, PMH0101, PMH0104, PMH0110 and PMK8850 PMIC
GPIOs with adding appropriate compatible strings.

Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: qcom,pmic-gpio: Add GPIO bindings for Glymur PMICs
Jishnu Prakash [Wed, 24 Sep 2025 17:01:02 +0000 (22:31 +0530)] 
dt-bindings: pinctrl: qcom,pmic-gpio: Add GPIO bindings for Glymur PMICs

Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation
to include compatible strings for PMK8850, PMH0101, PMH0104, PMH0110
and PMCX0102 PMICs.

Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: qcom: glymur: Fix the gpio and egpio pin functions
Abel Vesa [Fri, 19 Sep 2025 12:17:12 +0000 (15:17 +0300)] 
pinctrl: qcom: glymur: Fix the gpio and egpio pin functions

Mark the gpio/egpio as GPIO specific pin functions, othewise
the pin muxing generic framework will complain about the gpio
being already requested by a different owner.

Fixes: 87ebcd8baebf ("pinctrl: qcom: Add glymur pinctrl driver")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: qcom: glymur: Drop unnecessary platform data from match table
Abel Vesa [Fri, 19 Sep 2025 12:17:11 +0000 (15:17 +0300)] 
pinctrl: qcom: glymur: Drop unnecessary platform data from match table

The platform specific configuration is already passed on to the generic
msm probe. So it's useless to exist in the match table next to the
compatible. So drop it from match table.

Fixes: 87ebcd8baebf ("pinctrl: qcom: Add glymur pinctrl driver")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: qcom: msm8960: rename msmgpio node to tlmm
Antony Kurniawan Soemardi [Sun, 14 Sep 2025 18:34:59 +0000 (18:34 +0000)] 
dt-bindings: pinctrl: qcom: msm8960: rename msmgpio node to tlmm

Rename the GPIO controller node from "msmgpio" to "tlmm" to match the
convention used by other Qualcomm SoCs.

Suggested-by: Shinjo Park <peremen@gmail.com>
Signed-off-by: Antony Kurniawan Soemardi <linux@smankusors.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: pinctrl-single: add ti,am62l-padconf compatible
Bryan Brattlof [Fri, 12 Sep 2025 15:40:41 +0000 (10:40 -0500)] 
dt-bindings: pinctrl: pinctrl-single: add ti,am62l-padconf compatible

Add the "ti,am62l-padconf" compatible to allow for some changes in the
driver in the future when needed.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: mediatek: Add support for MT6878 pinctrl
Igor Belwon [Mon, 15 Sep 2025 12:46:25 +0000 (14:46 +0200)] 
pinctrl: mediatek: Add support for MT6878 pinctrl

Add driver support for the pin controller found in the MediaTek
Dimensity 7300 (MT6878) SoC.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: mediatek: Add debounce times for MT6878
Igor Belwon [Mon, 15 Sep 2025 12:46:24 +0000 (14:46 +0200)] 
pinctrl: mediatek: Add debounce times for MT6878

MT6878 uses different debounce times than other SoCs. Add them to the
EINT driver.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agodt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings
Igor Belwon [Mon, 15 Sep 2025 12:46:23 +0000 (14:46 +0200)] 
dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings

Add device-tree bindings for the pin controller and the EINT controller
found in the MediaTek MT6878 SoC.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 months agopinctrl: samsung: Add ARTPEC-9 SoC specific configuration
SeonGu Kang [Wed, 17 Sep 2025 07:00:04 +0000 (12:30 +0530)] 
pinctrl: samsung: Add ARTPEC-9 SoC specific configuration

Add Axis ARTPEC-9 SoC specific configuration data to enable pinctrl.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agodt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC
SeonGu Kang [Wed, 17 Sep 2025 07:00:03 +0000 (12:30 +0530)] 
dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC

Document the compatible string for ARTPEC-9 SoC pinctrl block,
which is similar to other Samsung SoC pinctrl blocks.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agopinctrl: samsung: add exynos8890 SoC pinctrl configuration
Ivaylo Ivanov [Sun, 14 Sep 2025 11:44:57 +0000 (14:44 +0300)] 
pinctrl: samsung: add exynos8890 SoC pinctrl configuration

Add support for the pin-controller found on the exynos8890 SoC, used in
Samsung Galaxy S7.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agodt-bindings: pinctrl: samsung: add exynos8890-wakeup-eint compatible
Ivaylo Ivanov [Sun, 14 Sep 2025 11:44:56 +0000 (14:44 +0300)] 
dt-bindings: pinctrl: samsung: add exynos8890-wakeup-eint compatible

Add a dedicated compatible for exynos8890.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agodt-bindings: pinctrl: samsung: add exynos8890 compatible
Ivaylo Ivanov [Sun, 14 Sep 2025 11:44:55 +0000 (14:44 +0300)] 
dt-bindings: pinctrl: samsung: add exynos8890 compatible

Document the pinctrl compatible for the exynos8890 SoC. Let the
driver handle our clocks for pinctrl as well.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agoLinux 6.18-rc1 v6.18-rc1
Linus Torvalds [Sun, 12 Oct 2025 20:42:36 +0000 (13:42 -0700)] 
Linux 6.18-rc1

2 months agoMerge tag 'i2c-for-6.18-rc1-hotfix' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 12 Oct 2025 20:27:56 +0000 (13:27 -0700)] 
Merge tag 'i2c-for-6.18-rc1-hotfix' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c fix from Wolfram Sang:
 "One revert because of a regression in the I2C core which has sadly not
  showed up during its time in -next"

* tag 'i2c-for-6.18-rc1-hotfix' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  Revert "i2c: boardinfo: Annotate code used in init phase only"

2 months agoMerge tag 'irq_urgent_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 12 Oct 2025 15:45:52 +0000 (08:45 -0700)] 
Merge tag 'irq_urgent_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Borislav Petkov:

 - Skip interrupt ID 0 in sifive-plic during suspend/resume because
   ID 0 is reserved and accessing reserved register space could result
   in undefined behavior

 - Fix a function's retval check in aspeed-scu-ic

* tag 'irq_urgent_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resume
  irqchip/aspeed-scu-ic: Fix an IS_ERR() vs NULL check

2 months agoMerge tag 'trace-v6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
Linus Torvalds [Sat, 11 Oct 2025 23:06:04 +0000 (16:06 -0700)] 
Merge tag 'trace-v6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull tracing fixes from Steven Rostedt:
 "The previous fix to trace_marker required updating trace_marker_raw as
  well. The difference between trace_marker_raw from trace_marker is
  that the raw version is for applications to write binary structures
  directly into the ring buffer instead of writing ASCII strings. This
  is for applications that will read the raw data from the ring buffer
  and get the data structures directly. It's a bit quicker than using
  the ASCII version.

  Unfortunately, it appears that our test suite has several tests that
  test writes to the trace_marker file, but lacks any tests to the
  trace_marker_raw file (this needs to be remedied). Two issues came
  about the update to the trace_marker_raw file that syzbot found:

   - Fix tracing_mark_raw_write() to use per CPU buffer

     The fix to use the per CPU buffer to copy from user space was
     needed for both the trace_maker and trace_maker_raw file.

     The fix for reading from user space into per CPU buffers properly
     fixed the trace_marker write function, but the trace_marker_raw
     file wasn't fixed properly. The user space data was correctly
     written into the per CPU buffer, but the code that wrote into the
     ring buffer still used the user space pointer and not the per CPU
     buffer that had the user space data already written.

   - Stop the fortify string warning from writing into trace_marker_raw

     After converting the copy_from_user_nofault() into a memcpy(),
     another issue appeared. As writes to the trace_marker_raw expects
     binary data, the first entry is a 4 byte identifier. The entry
     structure is defined as:

     struct {
    struct trace_entry ent;
    int id;
    char buf[];
     };

     The size of this structure is reserved on the ring buffer with:

       size = sizeof(*entry) + cnt;

     Then it is copied from the buffer into the ring buffer with:

       memcpy(&entry->id, buf, cnt);

     This use to be a copy_from_user_nofault(), but now converting it to
     a memcpy() triggers the fortify-string code, and causes a warning.

     The allocated space is actually more than what is copied, as the
     cnt used also includes the entry->id portion. Allocating
     sizeof(*entry) plus cnt is actually allocating 4 bytes more than
     what is needed.

     Change the size function to:

       size = struct_size(entry, buf, cnt - sizeof(entry->id));

     And update the memcpy() to unsafe_memcpy()"

* tag 'trace-v6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace:
  tracing: Stop fortify-string from warning in tracing_mark_raw_write()
  tracing: Fix tracing_mark_raw_write() to use buf and not ubuf

2 months agoMerge tag 'kbuild-fixes-6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sat, 11 Oct 2025 22:47:12 +0000 (15:47 -0700)] 
Merge tag 'kbuild-fixes-6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux

Pull Kbuild fixes from Nathan Chancellor:

 - Fix UAPI types check in headers_check.pl

 - Only enable -Werror for hostprogs with CONFIG_WERROR / W=e

 - Ignore fsync() error when output of gen_init_cpio is a pipe

 - Several little build fixes for recent modules.builtin.modinfo series

* tag 'kbuild-fixes-6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux:
  kbuild: Use '--strip-unneeded-symbol' for removing module device table symbols
  s390/vmlinux.lds.S: Move .vmlinux.info to end of allocatable sections
  kbuild: Add '.rel.*' strip pattern for vmlinux
  kbuild: Restore pattern to avoid stripping .rela.dyn from vmlinux
  gen_init_cpio: Ignore fsync() returning EINVAL on pipes
  scripts/Makefile.extrawarn: Respect CONFIG_WERROR / W=e for hostprogs
  kbuild: uapi: Strip comments before size type check

2 months agoRevert "i2c: boardinfo: Annotate code used in init phase only"
Wolfram Sang [Sat, 11 Oct 2025 10:31:53 +0000 (12:31 +0200)] 
Revert "i2c: boardinfo: Annotate code used in init phase only"

This reverts commit 1a2b423be6a89dd07d5fc27ea042be68697a6a49 because we
got a regression report and need time to find out the details.

Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Closes: https://lore.kernel.org/r/29ec0082-4dd4-4120-acd2-44b35b4b9487@oss.qualcomm.com
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2 months agoMerge tag 'rtc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Linus Torvalds [Sat, 11 Oct 2025 18:56:47 +0000 (11:56 -0700)] 
Merge tag 'rtc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

Pull RTC updates from Alexandre Belloni:
 "This cycle, we have a new RTC driver, for the SpacemiT P1. The optee
  driver gets alarm support. We also get a fix for a race condition that
  was fairly rare unless while stress testing the alarms.

  Subsystem:
   - Fix race when setting alarm
   - Ensure alarm irq is enabled when UIE is enabled
   - remove unneeded 'fast_io' parameter in regmap_config

  New driver:
   - SpacemiT P1 RTC

  Drivers:
   - efi: Remove wakeup functionality
   - optee: add alarms support
   - s3c: Drop support for S3C2410
   - zynqmp: Restore alarm functionality after kexec transition"

* tag 'rtc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (29 commits)
  rtc: interface: Ensure alarm irq is enabled when UIE is enabled
  rtc: tps6586x: Fix initial enable_irq/disable_irq balance
  rtc: cpcap: Fix initial enable_irq/disable_irq balance
  rtc: isl12022: Fix initial enable_irq/disable_irq balance
  rtc: interface: Fix long-standing race when setting alarm
  rtc: pcf2127: fix watchdog interrupt mask on pcf2131
  rtc: zynqmp: Restore alarm functionality after kexec transition
  rtc: amlogic-a4: Optimize global variables
  rtc: sd2405al: Add I2C address.
  rtc: Kconfig: move symbols to proper section
  rtc: optee: make optee_rtc_pm_ops static
  rtc: optee: Fix error code in optee_rtc_read_alarm()
  rtc: optee: fix error code in probe()
  dt-bindings: rtc: Convert apm,xgene-rtc to DT schema
  rtc: spacemit: support the SpacemiT P1 RTC
  rtc: optee: add alarm related rtc ops to optee rtc driver
  rtc: optee: remove unnecessary memory operations
  rtc: optee: fix memory leak on driver removal
  rtc: x1205: Fix Xicor X1205 vendor prefix
  dt-bindings: rtc: Fix Xicor X1205 vendor prefix
  ...

2 months agoMerge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Linus Torvalds [Sat, 11 Oct 2025 18:49:00 +0000 (11:49 -0700)] 
Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi

Pull SCSI fixes from James Bottomley:
 "Fixes only in drivers (ufs, mvsas, qla2xxx, target) that came in just
  before or during the merge window.

  The most important one is the qla2xxx which reverts a conversion to
  fix flexible array member warnings, that went up in this merge window
  but which turned out on further testing to be causing data corruption"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
  scsi: ufs: core: Include UTP error in INT_FATAL_ERRORS
  scsi: ufs: sysfs: Make HID attributes visible
  scsi: mvsas: Fix use-after-free bugs in mvs_work_queue
  scsi: ufs: core: Fix PM QoS mutex initialization
  scsi: ufs: core: Fix runtime suspend error deadlock
  Revert "scsi: qla2xxx: Fix memcpy() field-spanning write issue"
  scsi: target: target_core_configfs: Add length check to avoid buffer overflow

2 months agoMerge tag 'x86_core_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sat, 11 Oct 2025 18:19:16 +0000 (11:19 -0700)] 
Merge tag 'x86_core_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull more x86 updates from Borislav Petkov:

 - Remove a bunch of asm implementing condition flags testing in KVM's
   emulator in favor of int3_emulate_jcc() which is written in C

 - Replace KVM fastops with C-based stubs which avoids problems with the
   fastop infra related to latter not adhering to the C ABI due to their
   special calling convention and, more importantly, bypassing compiler
   control-flow integrity checking because they're written in asm

 - Remove wrongly used static branches and other ugliness accumulated
   over time in hyperv's hypercall implementation with a proper static
   function call to the correct hypervisor call variant

 - Add some fixes and modifications to allow running FRED-enabled
   kernels in KVM even on non-FRED hardware

 - Add kCFI improvements like validating indirect calls and prepare for
   enabling kCFI with GCC. Add cmdline params documentation and other
   code cleanups

 - Use the single-byte 0xd6 insn as the official #UD single-byte
   undefined opcode instruction as agreed upon by both x86 vendors

 - Other smaller cleanups and touchups all over the place

* tag 'x86_core_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
  x86,retpoline: Optimize patch_retpoline()
  x86,ibt: Use UDB instead of 0xEA
  x86/cfi: Remove __noinitretpoline and __noretpoline
  x86/cfi: Add "debug" option to "cfi=" bootparam
  x86/cfi: Standardize on common "CFI:" prefix for CFI reports
  x86/cfi: Document the "cfi=" bootparam options
  x86/traps: Clarify KCFI instruction layout
  compiler_types.h: Move __nocfi out of compiler-specific header
  objtool: Validate kCFI calls
  x86/fred: KVM: VMX: Always use FRED for IRQs when CONFIG_X86_FRED=y
  x86/fred: Play nice with invoking asm_fred_entry_from_kvm() on non-FRED hardware
  x86/fred: Install system vector handlers even if FRED isn't fully enabled
  x86/hyperv: Use direct call to hypercall-page
  x86/hyperv: Clean up hv_do_hypercall()
  KVM: x86: Remove fastops
  KVM: x86: Convert em_salc() to C
  KVM: x86: Introduce EM_ASM_3WCL
  KVM: x86: Introduce EM_ASM_1SRC2
  KVM: x86: Introduce EM_ASM_2CL
  KVM: x86: Introduce EM_ASM_2W
  ...

2 months agoMerge tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 11 Oct 2025 17:51:14 +0000 (10:51 -0700)] 
Merge tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Borislav Petkov:

 - Simplify inline asm flag output operands now that the minimum
   compiler version supports the =@ccCOND syntax

 - Remove a bunch of AS_* Kconfig symbols which detect assembler support
   for various instruction mnemonics now that the minimum assembler
   version supports them all

 - The usual cleanups all over the place

* tag 'x86_cleanups_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/asm: Remove code depending on __GCC_ASM_FLAG_OUTPUTS__
  x86/sgx: Use ENCLS mnemonic in <kernel/cpu/sgx/encls.h>
  x86/mtrr: Remove license boilerplate text with bad FSF address
  x86/asm: Use RDPKRU and WRPKRU mnemonics in <asm/special_insns.h>
  x86/idle: Use MONITORX and MWAITX mnemonics in <asm/mwait.h>
  x86/entry/fred: Push __KERNEL_CS directly
  x86/kconfig: Remove CONFIG_AS_AVX512
  crypto: x86 - Remove CONFIG_AS_VPCLMULQDQ
  crypto: X86 - Remove CONFIG_AS_VAES
  crypto: x86 - Remove CONFIG_AS_GFNI
  x86/kconfig: Drop unused and needless config X86_64_SMP

2 months agoMerge tag 'slab-for-6.18-rc1-hotfix' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 11 Oct 2025 17:40:24 +0000 (10:40 -0700)] 
Merge tag 'slab-for-6.18-rc1-hotfix' of git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab

Pull slab fix from Vlastimil Babka:
 "A NULL pointer deref hotfix"

* tag 'slab-for-6.18-rc1-hotfix' of git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab:
  slab: fix barn NULL pointer dereference on memoryless nodes

2 months agoMerge tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf
Linus Torvalds [Sat, 11 Oct 2025 17:31:38 +0000 (10:31 -0700)] 
Merge tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf

Pull bpf fixes from Alexei Starovoitov:

 - Finish constification of 1st parameter of bpf_d_path() (Rong Tao)

 - Harden userspace-supplied xdp_desc validation (Alexander Lobakin)

 - Fix metadata_dst leak in __bpf_redirect_neigh_v{4,6}() (Daniel
   Borkmann)

 - Fix undefined behavior in {get,put}_unaligned_be32() (Eric Biggers)

 - Use correct context to unpin bpf hash map with special types (KaFai
   Wan)

* tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf:
  selftests/bpf: Add test for unpinning htab with internal timer struct
  bpf: Avoid RCU context warning when unpinning htab with internal structs
  xsk: Harden userspace-supplied xdp_desc validation
  bpf: Fix metadata_dst leak __bpf_redirect_neigh_v{4,6}
  libbpf: Fix undefined behavior in {get,put}_unaligned_be32()
  bpf: Finish constification of 1st parameter of bpf_d_path()

2 months agoMerge tag 'mm-nonmm-stable-2025-10-10-15-03' of git://git.kernel.org/pub/scm/linux...
Linus Torvalds [Sat, 11 Oct 2025 17:27:52 +0000 (10:27 -0700)] 
Merge tag 'mm-nonmm-stable-2025-10-10-15-03' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm

Pull more updates from Andrew Morton:
 "Just one series here - Mike Rappoport has taught KEXEC handover to
  preserve vmalloc allocations across handover"

* tag 'mm-nonmm-stable-2025-10-10-15-03' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:
  lib/test_kho: use kho_preserve_vmalloc instead of storing addresses in fdt
  kho: add support for preserving vmalloc allocations
  kho: replace kho_preserve_phys() with kho_preserve_pages()
  kho: check if kho is finalized in __kho_preserve_order()
  MAINTAINERS, .mailmap: update Umang's email address

2 months agoMerge tag 'mm-hotfixes-stable-2025-10-10-15-00' of git://git.kernel.org/pub/scm/linux...
Linus Torvalds [Sat, 11 Oct 2025 17:14:55 +0000 (10:14 -0700)] 
Merge tag 'mm-hotfixes-stable-2025-10-10-15-00' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm

Pull misc fixes from Andrew Morton:
 "7 hotfixes.  All 7 are cc:stable and all 7 are for MM.

  All singletons, please see the changelogs for details"

* tag 'mm-hotfixes-stable-2025-10-10-15-00' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:
  mm: hugetlb: avoid soft lockup when mprotect to large memory area
  fsnotify: pass correct offset to fsnotify_mmap_perm()
  mm/ksm: fix flag-dropping behavior in ksm_madvise
  mm/damon/vaddr: do not repeat pte_offset_map_lock() until success
  mm/rmap: fix soft-dirty and uffd-wp bit loss when remapping zero-filled mTHP subpage to shared zeropage
  mm/thp: fix MTE tag mismatch when replacing zero-filled subpages
  memcg: skip cgroup_file_notify if spinning is not allowed

2 months agotracing: Stop fortify-string from warning in tracing_mark_raw_write()
Steven Rostedt [Sat, 11 Oct 2025 15:20:32 +0000 (11:20 -0400)] 
tracing: Stop fortify-string from warning in tracing_mark_raw_write()

The way tracing_mark_raw_write() records its data is that it has the
following structure:

  struct {
struct trace_entry;
int id;
char buf[];
  };

But memcpy(&entry->id, buf, size) triggers the following warning when the
size is greater than the id:

 ------------[ cut here ]------------
 memcpy: detected field-spanning write (size 6) of single field "&entry->id" at kernel/trace/trace.c:7458 (size 4)
 WARNING: CPU: 7 PID: 995 at kernel/trace/trace.c:7458 write_raw_marker_to_buffer.isra.0+0x1f9/0x2e0
 Modules linked in:
 CPU: 7 UID: 0 PID: 995 Comm: bash Not tainted 6.17.0-test-00007-g60b82183e78a-dirty #211 PREEMPT(voluntary)
 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.17.0-debian-1.17.0-1 04/01/2014
 RIP: 0010:write_raw_marker_to_buffer.isra.0+0x1f9/0x2e0
 Code: 04 00 75 a7 b9 04 00 00 00 48 89 de 48 89 04 24 48 c7 c2 e0 b1 d1 b2 48 c7 c7 40 b2 d1 b2 c6 05 2d 88 6a 04 01 e8 f7 e8 bd ff <0f> 0b 48 8b 04 24 e9 76 ff ff ff 49 8d 7c 24 04 49 8d 5c 24 08 48
 RSP: 0018:ffff888104c3fc78 EFLAGS: 00010292
 RAX: 0000000000000000 RBX: 0000000000000006 RCX: 0000000000000000
 RDX: 0000000000000000 RSI: 1ffffffff6b363b4 RDI: 0000000000000001
 RBP: ffff888100058a00 R08: ffffffffb041d459 R09: ffffed1020987f40
 R10: 0000000000000007 R11: 0000000000000001 R12: ffff888100bb9010
 R13: 0000000000000000 R14: 00000000000003e3 R15: ffff888134800000
 FS:  00007fa61d286740(0000) GS:ffff888286cad000(0000) knlGS:0000000000000000
 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
 CR2: 0000560d28d509f1 CR3: 00000001047a4006 CR4: 0000000000172ef0
 Call Trace:
  <TASK>
  tracing_mark_raw_write+0x1fe/0x290
  ? __pfx_tracing_mark_raw_write+0x10/0x10
  ? security_file_permission+0x50/0xf0
  ? rw_verify_area+0x6f/0x4b0
  vfs_write+0x1d8/0xdd0
  ? __pfx_vfs_write+0x10/0x10
  ? __pfx_css_rstat_updated+0x10/0x10
  ? count_memcg_events+0xd9/0x410
  ? fdget_pos+0x53/0x5e0
  ksys_write+0x182/0x200
  ? __pfx_ksys_write+0x10/0x10
  ? do_user_addr_fault+0x4af/0xa30
  do_syscall_64+0x63/0x350
  entry_SYSCALL_64_after_hwframe+0x76/0x7e
 RIP: 0033:0x7fa61d318687
 Code: 48 89 fa 4c 89 df e8 58 b3 00 00 8b 93 08 03 00 00 59 5e 48 83 f8 fc 74 1a 5b c3 0f 1f 84 00 00 00 00 00 48 8b 44 24 10 0f 05 <5b> c3 0f 1f 80 00 00 00 00 83 e2 39 83 fa 08 75 de e8 23 ff ff ff
 RSP: 002b:00007ffd87fe0120 EFLAGS: 00000202 ORIG_RAX: 0000000000000001
 RAX: ffffffffffffffda RBX: 00007fa61d286740 RCX: 00007fa61d318687
 RDX: 0000000000000006 RSI: 0000560d28d509f0 RDI: 0000000000000001
 RBP: 0000560d28d509f0 R08: 0000000000000000 R09: 0000000000000000
 R10: 0000000000000000 R11: 0000000000000202 R12: 0000000000000006
 R13: 00007fa61d4715c0 R14: 00007fa61d46ee80 R15: 0000000000000000
  </TASK>
 ---[ end trace 0000000000000000 ]---

This is because fortify string sees that the size of entry->id is only 4
bytes, but it is writing more than that. But this is OK as the
dynamic_array is allocated to handle that copy.

The size allocated on the ring buffer was actually a bit too big:

  size = sizeof(*entry) + cnt;

But cnt includes the 'id' and the buffer data, so adding cnt to the size
of *entry actually allocates too much on the ring buffer.

Change the allocation to:

  size = struct_size(entry, buf, cnt - sizeof(entry->id));

and the memcpy() to unsafe_memcpy() with an added justification.

Cc: stable@vger.kernel.org
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lore.kernel.org/20251011112032.77be18e4@gandalf.local.home
Fixes: 64cf7d058a00 ("tracing: Have trace_marker use per-cpu data to read user space")
Reported-by: syzbot+9a2ede1643175f350105@syzkaller.appspotmail.com
Closes: https://lore.kernel.org/all/68e973f5.050a0220.1186a4.0010.GAE@google.com/
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
2 months agoslab: fix barn NULL pointer dereference on memoryless nodes
Vlastimil Babka [Sat, 11 Oct 2025 08:45:41 +0000 (10:45 +0200)] 
slab: fix barn NULL pointer dereference on memoryless nodes

Phil reported a boot failure once sheaves become used in commits
59faa4da7cd4 ("maple_tree: use percpu sheaves for maple_node_cache") and
3accabda4da1 ("mm, vma: use percpu sheaves for vm_area_struct cache"):

 BUG: kernel NULL pointer dereference, address: 0000000000000040
 #PF: supervisor read access in kernel mode
 #PF: error_code(0x0000) - not-present page
 PGD 0 P4D 0
 Oops: Oops: 0000 [#1] SMP NOPTI
 CPU: 21 UID: 0 PID: 818 Comm: kworker/u398:0 Not tainted 6.17.0-rc3.slab+ #5 PREEMPT(voluntary)
 Hardware name: Dell Inc. PowerEdge R7425/02MJ3T, BIOS 1.26.0 07/30/2025
 RIP: 0010:__pcs_replace_empty_main+0x44/0x1d0
 Code: ec 08 48 8b 46 10 48 8b 76 08 48 85 c0 74 0b 8b 48 18 85 c9 0f 85 e5 00 00 00 65 48 63 05 e4 ee 50 02 49 8b 84 c6 e0 00 00 00 <4c> 8b 68 40 4c 89 ef e8 b0 81 ff ff 48 89 c5 48 85 c0 74 1d 48 89
 RSP: 0018:ffffd2d10950bdb0 EFLAGS: 00010246
 RAX: 0000000000000000 RBX: ffff8a775dab74b0 RCX: 00000000ffffffff
 RDX: 0000000000000cc0 RSI: ffff8a6800804000 RDI: ffff8a680004e300
 RBP: ffffd2d10950be40 R08: 0000000000000060 R09: ffffffffb9367388
 R10: 00000000000149e8 R11: ffff8a6f87a38000 R12: 0000000000000cc0
 R13: 0000000000000cc0 R14: ffff8a680004e300 R15: 00000000000000c0
 FS:  0000000000000000(0000) GS:ffff8a77a3541000(0000) knlGS:0000000000000000
 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
 CR2: 0000000000000040 CR3: 0000000e1aa24000 CR4: 00000000003506f0
 Call Trace:
  <TASK>
  ? srso_return_thunk+0x5/0x5f
  ? vm_area_alloc+0x1e/0x60
  kmem_cache_alloc_noprof+0x4ec/0x5b0
  vm_area_alloc+0x1e/0x60
  create_init_stack_vma+0x26/0x210
  alloc_bprm+0x139/0x200
  kernel_execve+0x4a/0x140
  call_usermodehelper_exec_async+0xd0/0x190
  ? __pfx_call_usermodehelper_exec_async+0x10/0x10
  ret_from_fork+0xf0/0x110
  ? __pfx_call_usermodehelper_exec_async+0x10/0x10
  ret_from_fork_asm+0x1a/0x30
  </TASK>
 Modules linked in:
 CR2: 0000000000000040
 ---[ end trace 0000000000000000 ]---
 RIP: 0010:__pcs_replace_empty_main+0x44/0x1d0
 Code: ec 08 48 8b 46 10 48 8b 76 08 48 85 c0 74 0b 8b 48 18 85 c9 0f 85 e5 00 00 00 65 48 63 05 e4 ee 50 02 49 8b 84 c6 e0 00 00 00 <4c> 8b 68 40 4c 89 ef e8 b0 81 ff ff 48 89 c5 48 85 c0 74 1d 48 89
 RSP: 0018:ffffd2d10950bdb0 EFLAGS: 00010246
 RAX: 0000000000000000 RBX: ffff8a775dab74b0 RCX: 00000000ffffffff
 RDX: 0000000000000cc0 RSI: ffff8a6800804000 RDI: ffff8a680004e300
 RBP: ffffd2d10950be40 R08: 0000000000000060 R09: ffffffffb9367388
 R10: 00000000000149e8 R11: ffff8a6f87a38000 R12: 0000000000000cc0
 R13: 0000000000000cc0 R14: ffff8a680004e300 R15: 00000000000000c0
 FS:  0000000000000000(0000) GS:ffff8a77a3541000(0000) knlGS:0000000000000000
 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
 CR2: 0000000000000040 CR3: 0000000e1aa24000 CR4: 00000000003506f0
 Kernel panic - not syncing: Fatal exception
 Kernel Offset: 0x36a00000 from 0xffffffff81000000 (relocation range: 0xffffffff80000000-0xffffffffbfffffff)
 ---[ end Kernel panic - not syncing: Fatal exception ]---

And noted "this is an AMD EPYC 7401 with 8 NUMA nodes configured such
that memory is only on 2 of them."

 # numactl --hardware
 available: 8 nodes (0-7)
 node 0 cpus: 0 8 16 24 32 40 48 56 64 72 80 88
 node 0 size: 0 MB
 node 0 free: 0 MB
 node 1 cpus: 2 10 18 26 34 42 50 58 66 74 82 90
 node 1 size: 31584 MB
 node 1 free: 30397 MB
 node 2 cpus: 4 12 20 28 36 44 52 60 68 76 84 92
 node 2 size: 0 MB
 node 2 free: 0 MB
 node 3 cpus: 6 14 22 30 38 46 54 62 70 78 86 94
 node 3 size: 0 MB
 node 3 free: 0 MB
 node 4 cpus: 1 9 17 25 33 41 49 57 65 73 81 89
 node 4 size: 0 MB
 node 4 free: 0 MB
 node 5 cpus: 3 11 19 27 35 43 51 59 67 75 83 91
 node 5 size: 32214 MB
 node 5 free: 31625 MB
 node 6 cpus: 5 13 21 29 37 45 53 61 69 77 85 93
 node 6 size: 0 MB
 node 6 free: 0 MB
 node 7 cpus: 7 15 23 31 39 47 55 63 71 79 87 95
 node 7 size: 0 MB
 node 7 free: 0 MB

Linus decoded the stacktrace to get_barn() and get_node() and determined
that kmem_cache->node[numa_mem_id()] is NULL.

The problem is due to a wrong assumption that memoryless nodes only
exist on systems with CONFIG_HAVE_MEMORYLESS_NODES, where numa_mem_id()
points to the nearest node that has memory. SLUB has been allocating its
kmem_cache_node structures only on nodes with memory and so it does with
struct node_barn.

For kmem_cache_node, get_partial_node() checks if get_node() result is
not NULL, which I assumed was for protection from a bogus node id passed
to kmalloc_node() but apparently it's also for systems where
numa_mem_id() (used when no specific node is given) might return a
memoryless node.

Fix the sheaves code the same way by checking the result of get_node()
and bailing out if it's NULL. Note that cpus on such memoryless nodes
will have degraded sheaves performance, which can be improved later,
preferably by making numa_mem_id() work properly on such systems.

Fixes: 2d517aa09bbc ("slab: add opt-in caching layer of percpu sheaves")
Reported-and-tested-by: Phil Auld <pauld@redhat.com>
Closes: https://lore.kernel.org/all/20251010151116.GA436967@pauld.westford.csb/
Analyzed-by: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/all/CAHk-%3Dwg1xK%2BBr%3DFJ5QipVhzCvq7uQVPt5Prze6HDhQQ%3DQD_BcQ@mail.gmail.com/
Signed-off-by: Vlastimil Babka <vbabka@suse.cz>
2 months agotracing: Fix tracing_mark_raw_write() to use buf and not ubuf
Steven Rostedt [Sat, 11 Oct 2025 03:51:42 +0000 (23:51 -0400)] 
tracing: Fix tracing_mark_raw_write() to use buf and not ubuf

The fix to use a per CPU buffer to read user space tested only the writes
to trace_marker. But it appears that the selftests are missing tests to
the trace_maker_raw file. The trace_maker_raw file is used by applications
that writes data structures and not strings into the file, and the tools
read the raw ring buffer to process the structures it writes.

The fix that reads the per CPU buffers passes the new per CPU buffer to
the trace_marker file writes, but the update to the trace_marker_raw write
read the data from user space into the per CPU buffer, but then still used
then passed the user space address to the function that records the data.

Pass in the per CPU buffer and not the user space address.

TODO: Add a test to better test trace_marker_raw.

Cc: stable@vger.kernel.org
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lore.kernel.org/20251011035243.386098147@kernel.org
Fixes: 64cf7d058a00 ("tracing: Have trace_marker use per-cpu data to read user space")
Reported-by: syzbot+9a2ede1643175f350105@syzkaller.appspotmail.com
Closes: https://lore.kernel.org/all/68e973f5.050a0220.1186a4.0010.GAE@google.com/
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>