configs: Increase USB Hub debounce timeout in Agilex5
Some legacy USB mass storage devices during connection were
observed to have debounce issues. Hence, increasing the default
USB Hub debounce timeout value to handle this issue for devices
connected to Agilex5 boards.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: clk: agilex: Support for enable/disable API
Update Agilex clock driver to support enabling or disabling
the peripheral clocks via clock driver model APIs.
The caller will pass the clock ID to this driver and the driver
will then proceed to manipulate the desired bit in the Agilex clock
manager peripheral PLL register based on the given clock ID.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Boon Khai Ng [Thu, 14 Aug 2025 03:17:40 +0000 (11:17 +0800)]
cache: Check dcache availability before calling cache functions
When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.
Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).
Without this check, builds with dcache disabled will fail to compile.
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Boon Khai Ng [Thu, 14 Aug 2025 03:17:39 +0000 (11:17 +0800)]
arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in smc_send_mailbox()
Adding the dcache flushing and invalidation in the smc_send_mailbox()
At the same time replace the use of u64 with uintptr_t to ensure
compatibility across different architectures and correct the
pointer arithmetic for buffer end address calculation.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations
The QSPI mailbox API function declarations (mbox_qspi_close and
mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI
preprocessor conditional. This prevented their prototypes from being
visible to code that may use the stub implementations when
CONFIG_CADENCE_QSPI is disabled.
Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions
are always declared, regardless of the configuration. This avoids potential
build or linkage errors when stubs are used.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: Define Use FPGA switch handoff section size for Agilex5
Agilex5 FPGA switch section in the handoff data is larger by 32 bytes
than the default value as these extra sections contains I3C0 and I3C1
register offsets and values with 4 bytes each.
This requires 4 more times of reading the FPGA switch section of the
handoff data to fully populate the handoff data table in the memory
during runtime.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: ddr: altera: Correct DDR calibration status check
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Compatibility check of IOSSM mailbox with U-Boot is performed
by verifying the mailbox specification version. If check fails,
appropriate error message is displayed.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
configs: socfpga: Remove SYS_BOOTM_LEN from N5X VAB config
Remove the current CONFIG_SYS_BOOTM_LEN in N5X VAB defconfig.
Previously, the size was set to 32MB, but due to larger kernel image,
64MB size is required. This 64MB configuration has been set as
default in the Kconfig.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
To ensure unintentional bugs occurring because of config changes
in master defconfig and its VAB variants, VAB defconfig files now
include the master defconfig and enable config values specific to
VAB functionality only.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: dts: socfpga: Enable driver model for watchdog timer
All SoCFPGA platforms are switching to CONFIG_WDT (driver
model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status
of watchdog is enabled to assist with this switching.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch: arm: dts: agilex5: Disable cache allocation for reads
In order to circumvent CCU NOC issue in Agilex5, it is recommended
to disable cache allocation for reads. This prevents hang issues
caused by CCP (Common Cache Pipe) Fill Done FIFO overflow.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
While it is good that the "Licenses/" directory contains the text
for all licenses that are applicable to u-boot code, it is harder
to determine at a glance what the default and/or preferred license
is. While humans can look at the Licenses/README file, this is not
machine parseable, making it tricky for license detection tools to
automatically determine/report on the overall / aggregate u-boot
license.
The project previously had a top level COPYING file containing a
short blurb, followed by the GPL license text. This was removed
back in commit eca3aeb352c964bdb28b8e191d6326370245e03f when
the "Licenses/" directory was introduced. For the benefit of
automated tools, it is helpful to retain a top level COPYING
file in the repository. Rather than duplicate the license text,
however, a symlink from the Licenses/gpl-2.0.txt file should
suffice.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reported-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Tom Rini <trini@konsulko.com>
* Correct encodings for spl memory layout diagrams
* Suggest usage of KDOC_WERROR when building documentation
* Replace references to README.fdt-control
* Clarify precedence of environment locations
* Add documentation for the TI am335x_evm board
* Remove README.commands.itest
* Add a note about asking for feedback in the development process
Michal Simek [Wed, 24 Sep 2025 14:18:18 +0000 (16:18 +0200)]
efi_loader: Cleanup UEFI Variables menu selection
There are 3 options listed between choice/endchoice FILE/TEE/NO_STORE.
There is no reason to add other config with dependencies between
choice/endchoice because they can never be selected because they depends on
only that 3 options which can be selected.
That's why move additional configuration with dependency below choice
section.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tom Rini [Tue, 23 Sep 2025 17:54:29 +0000 (11:54 -0600)]
doc: develop: process: Add note about asking for feedback
It can be unclear to contributors what to do if they haven't gotten any
feedback on patches they have submitted. Add a sentence saying that if
they feel it's been too long without any comment, it's OK to reply
again.
doc: memory: fix encodings for spl layout diagrams
The commit 284ef1bbcefc ("doc: memory: Add documentation for system
RAM") added documentation for U-Boot's memory usage along with diagrams
showcasing the SPL's memory usage. Although the SVGs for the diagrams
were improperly encoded.
Therefore, this patch fixes the older SVGs with one's with better
encoding and reduced size created using inkscape[1].
[1]: https://inkscape.org/
Reported-by: Alexander Dahl <ada@thorsis.com> Fixes: 284ef1bbcefc ("doc: memory: Add documentation for system RAM") Signed-off-by: Anshul Dalal <anshuld@ti.com>
Since commit 5cf6a06a it is possible to have both text-based and
old-style C environment files. But so far the environment documentation
has not reflected this change. This commit fixes that.
Signed-off-by: Ricardo Simoes <ricardo.simoes@pt.bosch.com> Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Tom Rini [Fri, 12 Sep 2025 23:02:52 +0000 (17:02 -0600)]
doc: Remove README.commands.itest
We currently document this command in doc/usage/cmd/itest.rst and this
documentation is more comprehensive than the older README file. Delete
the older file.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
When applying the patch that became commit a2d881f5bcd3 ("doc: memory:
Add documentation for system RAM") one of the diagrams was missed.
Re-add this missing file.
Reported-by: Adriano Carvalho <adrianocarvalho.pt@gmail.com> Fixes: a2d881f5bcd3 doc: memory: Add documentation for system RAM Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[trini: Take Neha's original svg and re-apply it] Signed-off-by: Tom Rini <trini@konsulko.com>
Peng Fan [Fri, 26 Sep 2025 01:57:47 +0000 (09:57 +0800)]
MAINTAINERS: Update MMC/POWER/FREESCALE QORIQ
- Update MMC entry to match 'mmc' using 'N'
- Add myself as POWER maintainer for regulator and pmic patches. I have
started to handle relevant patches.
- Update QORIQ maintainer. Priyanka has moved to work on other stuff, I
have been handling this for quite some time.
Add myself as a maintainer of the NETWORK subsystem since:
- I have effectively been handling net patches in my patchwork queue and
sending pull requests to Tom,
- I do have push access to the u-boot-net custodian tree.
Also, add u-boot-net as the SCM tree for NETWORK (LWIP) since it is where
lwIP-related patches end up too.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> CC: Ramon Fried <rfried.dev@gmail.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Tom Rini <trini@konsulko.com>
Marek Vasut [Wed, 24 Sep 2025 01:47:14 +0000 (03:47 +0200)]
pci: pcie-rcar-gen4: Add missing 1ms delay after PWR reset assertion
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.
Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.
This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Wed, 24 Sep 2025 01:47:13 +0000 (03:47 +0200)]
pci: pcie-rcar-gen4: Assure reset occurs before DBI access
Assure the reset is latched and the core is ready for DBI access.
On R-Car V4H, the PCIe reset is asynchronized and does not take
effect immediately, but needs a short time to complete. In case
DBI access happens in that short time, that access generates an
SError. Make sure that condition can never happen, read back the
state of the reset which should turn the asynchronized reset into
synchronized one, and wait a little over 1ms to add additional
safety margin.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Wed, 24 Sep 2025 01:47:12 +0000 (03:47 +0200)]
pci: pcie-rcar-gen4: Fix inverted break condition in PHY initialization
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
indicates that register 0xf8 should be polled until bit 18 becomes set to 1.
Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
condition is inverted and returns when register 0xf8 bit 18 is set to 0,
which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
the timing changes just enough for the first readl_poll_timeout() poll to
already read register 0xf8 bit 18 as 1 and afterward never read register
0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
controller.
Fix this by inverting the poll condition to match the reference manual
initialization sequence.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
board: rzg2l: Check the DTB pointer passed by the TF-A.
On the RZG2L platform, the advised
TF-A (https://github.com/renesas-rz/rzg_trusted-firmware-a/tree/v2.5/rzg2l)
does not pass any DTB blob to U-Boot.
On the other hand, the RZG2L part of U-Boot expects a DTB to be passed. It
means that if one flashes the latest TF-A as well as the mainline U-Boot,
it will crash trying to dereference the NULL DTB pointer before outputing
anything.
Check if the DTB pointer is NULL before trying to use it.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
board: phytec: common: Fix missing newline in error message
The error message in phytec_get_product_name() was missing a newline,
causing log output to be concatenated with subsequent messages. Add
the newline to improve readability.
After switching our boards to standard boot, we observed that the
kernel hangs when booting with the "script" boot method over the
network.
The original scriptaddr value was copied from ti_common.env and
remained unused for some time. On phycore-am62x and phycore-am62ax,
however, this address conflicts with the current location where
ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR).
Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r.
The phycore-am64x is not affected by this issue, but we update it
as well to keep all phycore-am6xx boards consistent.
- Fix Phycore i.MX93 voltage modes
- Call DM post init function for init_r phase on i.MX8ULP
- Fix ELE FW version print bug on i.MX8UL EVK.
- Fix LPCG number in ccm_reg structure on i.MX93
board: phytec: phycore-imx93: Fix i.MX93 voltage modes
Fix support for i.MX93 voltage modes on phyCORE-i.MX93 SoM boards.
First of all, Kconfig option CONFIG_IMX9_LOW_DRIVE_MODE is gone since
commit c9efcad23741 ("imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and
ld defconfig") and was replaced by runtime detection mechanism. Thus
lets use is_voltage_mode() instead of Kconfig to detect CPU type and
select proper voltage mode.
Secondly, 1400MHz ND mode (Nominal Drive) requiring 0.85V BUCK voltage
was not supported with current power_init_board() PMIC settings. Add
check also for this CPU type and set BUCK voltage accordingly.
Last but not least, add printf() printouts about PMIC voltage mode to
the console. This makes it more apparent and verbose about voltage mode
in use. Also our internal tests depend on this printout to catch issues
with i.MX93 CPU types and set PMIC voltage modes.
Ye Li [Fri, 19 Sep 2025 06:58:34 +0000 (14:58 +0800)]
arm: imx9: Fix LPCG number in ccm_reg structure
The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong
value is used in ccm_reg structure and Coverity reports several
issues as out-of-bounds write.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 19 Sep 2025 06:58:33 +0000 (14:58 +0800)]
imx8ulp_evk: Fix ELE FW version print bug
According to latest ELE Get FW version API, the FW version word is defined
as below. The patch version only has 4 bits and minor version has 12 bits.
However, the codes use 8 bits for patch version and minor version. Add the
patch to fix the issue.
ELE firmware version
[31] - When set indicates a dirty build.
[30] - Reserved
[29:28] - Hotfix version.
[27] - When set, indicate that ELE FW is authenticated and operational.
[26:25] - Reserved
[24] - When set, indicate that an alternative FW is running.
[23:16] - Indicate the major version. This byte is checked against the
version set in the fuses to determine if the FW execution can be authorized
[15:4] - Indicate the minor version.
[3:0] - Indicate the patch version.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Sun, 7 Sep 2025 01:00:47 +0000 (03:00 +0200)]
board: dhelectronics: Use isascii() before isprint() in dh_read_eeprom_id_page()
The isprint() checks printability across all 256 characters, some of the
upper 128 characters are printable and produce artifacts on UART. Call
isascii() first to only consider the bottom 7bit ASCII characters as
printable, and then check their printability using isprint(). This fixes
a rare misprint in case the ID page content is uninitialized or corrupted.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Marek Vasut [Sun, 7 Sep 2025 01:00:46 +0000 (03:00 +0200)]
board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()
The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL.
The current NULL pointer check happens too late, after the eip was
accessed in variable assignment. Reorder the two, so the NULL pointer
check happens first, and any access second, otherwise the access may
trigger a hang or other undefined behavior.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Tom Rini [Wed, 17 Sep 2025 13:52:31 +0000 (07:52 -0600)]
Merge patch series "Hyperflash boot fixes for j721e/j7200"
Anurag Dutta <a-dutta@ti.com> says:
This series introdues a couple of small fixes that involves
enabling hyperflash at R5 SPL and u-boot proper stage and
Kconfig changes that are required for HBMC boot on j721e/j7200
Michal Simek [Wed, 17 Sep 2025 07:22:18 +0000 (09:22 +0200)]
xilinx: Disable SPL_OS_BOOT for Zynq and ZynqMP
The commit 210702ae6ce8 ("spl: spi: fix falcon mode for spi boot") fixed
the logic of spl_start_uboot() where 0 means OS boot and 1 means u-boot.
Zynq/ZynqMP enable OS_BOOT by default but it was never really be used
that's why disable it to boot via U-Boot phase all the time.
Signed-off-by: Michal Simek <michal.simek@amd.com>
board: ti: am57xx: Remove "ti/omap/" from name_fit_config
Commit 649f4a7d3ca7 ("board: ti: am57xx: Set fdtfile from C code
instead of findfdt script") prepends "ti/omap/" to the actual name
of the fdtfile whereas fit image boot needs exact dtb name. So, remove
"ti/omap" from name_fit_config by substituting it with an empty string.
Fixes: 649f4a7d3ca7 ("board: ti: am57xx: Set fdtfile from C code instead of findfdt script") Signed-off-by: Anurag Dutta <a-dutta@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Alice Guo [Fri, 5 Sep 2025 18:22:04 +0000 (02:22 +0800)]
imx95_evk: Restore support for i.MX95 A0 silicon
This patch is used to restore support for i.MX95 A0 silicon. To avoid
duplicating defconfig, imx95.config is added and can be shared between
imx95_a0_19x19_evk_defconfig and imx95_19x19_evk_defconfig.
container.cfg and imximage.cfg are used to created .cfgout files that
are be passed to mkimage with -n to build flash.bin. Now they have been
deleted and replaced by adding their content to properties of node which
type is nxp-imx9image under binman node.
Fixes: 9936724aa9b ("imx95_evk: Add i.MX95 B0 support") Signed-off-by: Alice Guo <alice.guo@nxp.com> Tested-By: Tim Harvey <tharvey@gateworks.com> # imx95-19x19-evk (rA0)
Alice Guo [Fri, 5 Sep 2025 18:22:03 +0000 (02:22 +0800)]
binman: add a new entry type to support .bin file generation for the i.MX95 platform
To support passing specific commands defined in enum imx8image_cmd to
the imx8image_copy_image() function, this patch introduces a new entry
type nxp-imx9image. This entry generates a plain text data file
containing the relevant commands, enabling flexible configuration during
image creation.
Per recent discussion [1] product IDs VF7110A or VF7110B from EEPROM are
sufficient to select for VisionFive 2 1.2a or VisionFive 2 1.3b boards.
There are no VisionFive 2 products with mixed-case product IDs in EERPOM
so factor out the unnecessary select case conditional.
Marek Vasut [Mon, 15 Sep 2025 00:49:05 +0000 (02:49 +0200)]
ARM: stm32: Perform node compatible check for KS8851 early
Check the compatible string of ethernet1 node for KS8851 very early on,
before calling uclass_get_device_by_of_path() which might initialize
the device and possibly attempt to configure MAC address into device
which is not KS8851. Doing the compatibility check early prevent this.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Mon, 15 Sep 2025 00:53:04 +0000 (02:53 +0200)]
net: dwc_eth_qos: Fix support for stm32mp2 platform
The layout of SYSCFG_ETHnCR on STM32MP25xx is slightly different yet again.
Add missing swizzling to program the correct register with the correct content.
Fixes: 20afca89ed53 ("net: dwc_eth_qos: add support of stm32mp2 platform") Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Christophe ROULLIER<christophe.roullier@foss.st.com>
Marek Vasut [Sat, 6 Sep 2025 23:00:01 +0000 (01:00 +0200)]
clk: stm32: Pass udevice pointer to clk_register_composite()
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Ye Li [Fri, 12 Sep 2025 09:41:11 +0000 (17:41 +0800)]
arm: armv8: Fix spl recover data section broken
SPL recover data section is broken which causes reboot failure on
some i.MX platforms (iMX8QM/iMX95).
The global variable cold_reboot_flag is assigned to weak reset_flag
function which always return 1, so restore never been executed in
warm reboot.
Fixes: 1c37e59bfbba ("arm: armv8: Improve SPL data save and restore implementation") Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
spl_start_uboot is a board overridable function that switches to falcon
boot mode on return value of 0.
Though for SPI, the falcon boot mode was being enabled on return value
of 1 which is not the correct behaviour. Therefore this patch fixes it
to the expected boot flow.
Tom Rini [Thu, 11 Sep 2025 16:03:12 +0000 (10:03 -0600)]
Merge patch series "Fix dma_addr_t for R5 SPL"
Anshul Dalal <anshuld@ti.com> says:
On various TI's K3 platforms boot failure was observed on SPI NOR since the
commit 5609f200d062 ("arm: Kconfig: enable LTO for ARCH_K3"). This issue was
root caused to stack corruption by the 'udma_transfer' function. Where the local
variable 'paddr' of type 'dma_addr_t' was being written to as a 64-bit value
which overwrote the stack frame of the caller (dma_memcpy) as only 32-bits had
been reserved for paddr on the stack, specifically the r4 register in the frame
of dma_memcpy was being overwritten with a 0.
drivers/dma/ti/k3-udma.c:2192:
int udma_transfer(...)
{
...
dma_addr_t paddr = 0;
...
/* paddr was written to as 64-bit value here */
udma_poll_completion(uc, &paddr);
}
drivers/dma/dma-uclass.c:234:
int dma_memcpy(...)
{
dma_addr_t destination;
dma_addr_t source;
int ret;
...
/* This call resolves to udma_transfer */
ret = ops->transfer(...);
Enabling LTO changed how gcc mapped local variables of dma_memcpy to CPU
registers, where earlier the bug was hidden since the overwritten register
'r4' was allotted to 'ret' but was allotted to 'destination' once LTO was
enabled. And since the overwritten value was 0, the bug remained undetected
as it just meant ret was 0, but having 'destination' set to 0 caused
dma_unmap_single to fail silently leading to boot failures.
The fix entails enabling DMA_ADDR_T_64BIT which changes dma_addr_t from u32 to
u64 for the R5 SPL thus reserving enough space for 'paddr' to prevent the
overflow.
ARCH_K3 encompasses both 32 and 64-bit cores on the same SoC, though the
DMA addresses are always 64-bit in size.
With the current implementation, the R5 SPL uses a u32 for dma_addr_t
which leads to data overflow when functions such as k3_nav_*_pop_mem try
to write a 64-bit address to dma_addr_t variable.
In certain cases it leads to stack corruption which manifest as boot
failures on certain compilers, such as SPI boot on GCC 14.2 or 13.3.
Therefore this patch selects CONFIG_DMA_ADDR_T_64BIT for all ARCH_K3.
dma_addr_t is used to store any valid DMA address which might not
necessarily be the same size as host architecture's word size. Though
various typecasts in k3's dma and usb driver expect dma_addr_t to be the
same size as the word size.
This leads the compiler to throw a "cast from pointer to integer of
different size" warning when the condition is not met, for example when
enabling CONFIG_DMA_ADDR_T_64BIT for the R5 core.
Therefore this patch fixes the typecasts by using 'uintptr_t' as an
intermediary type which is guaranteed to be the same size as void* on
the host architecture. Thus, eliminating the compiler warning.
env: fix config dependency for ENV_OFFSET_REDUND_RELATIVE_END
Since commit 5fb88fa725 "env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDANT"
the option SYS_REDUNDAND_ENVIRONMENT is no longer available and should be
renamed to ENV_REDUNDANT.
Fixes: 95f03ee65c0e ("env: mmc: fix offsets relative to the end of the partition") Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Tom Rini <trini@konsulko.com>
The SPI flash driver does not build without SPI support enabled.
Fixes: 4151f4f822bb ("spl: Rework and tighten some dependencies") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Anshul Dalal <anshuld@ti.com>
Enable CONFIG_DNS for visionfive2 board target. With CONFIG_PROT_DNS_LWIP
enabled and CONFIG_CMD_DNS disabled this restores DNS functionality
displaced by LwIP DNS refactoring during the merge window.
Patrick Rudolph [Wed, 3 Sep 2025 07:05:01 +0000 (09:05 +0200)]
configs: Fix crash on coreboot x86
Booting u-boot as payload with coreboot's main branch is currently broken
since commit [1] on x86 as U-boot assumes the active GDT matches what
U-Boot would have installed in start16.S.
Make no assumptions and always load the GDT when building as coreboot
payload to make sure the segment registers are actually matching the GDT.
Fixes #GP seen when booting U-Boot as coreboot payload.
include: env: ti: Use .env for environment variables
Add omap common environment variables to .env. We retain the old-style C
environment .h files to maintain compatibility with other omap devices that
have not moved to using .env yet.
Marek Vasut [Wed, 3 Sep 2025 11:23:23 +0000 (13:23 +0200)]
arm64: renesas: r8a779g3: Use $loadaddr in bootcmd on Retronix R-Car V4H Sparrow Hawk board
Avoid use of hard-coded address in boot command, instead use $loadaddr
which is the default load address. This improves consistency of the
environment on this board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Wed, 3 Sep 2025 11:23:57 +0000 (13:23 +0200)]
ARM: renesas: Enable CONFIG_ENV_VARS_UBOOT_CONFIG on all boards
The CONFIG_ENV_VARS_UBOOT_CONFIG extends U-Boot environment with
variables arch/board/board_name/soc/vendor, which can be used to
discern different devices from each other based purely on U-Boot
environment variables.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Andrew Goodbody [Mon, 1 Sep 2025 15:13:14 +0000 (16:13 +0100)]
spi: exynos: Remove extra term from test
In spi_rx_tx there comes a test for execution of a code block that
allows execution if rxp is not NULL or stopping is true. However all the
code in this block relies on rxp being valid so allowing entry just if
stopping is true does not make sense. So remove this from the test
expression leaving just a NULL check for rxp.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andrew Goodbody [Thu, 7 Aug 2025 14:41:18 +0000 (15:41 +0100)]
pinctrl: rzg2l: Variable may not have been assigned to
In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Paul Barker <paul@pbarker.dev> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
projects / thirdparty / u-boot.git / log
