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11 months agogdb: add target_fileio_stat, but no implementations yet
Andrew Burgess [Tue, 21 May 2024 14:39:37 +0000 (15:39 +0100)] 
gdb: add target_fileio_stat, but no implementations yet

In a later commit I want target_fileio_stat, that is a call that
operates on a filename rather than an open file descriptor as
target_fileio_fstat does.

This commit adds the initial framework for target_fileio_stat, I've
added the top level target function and the virtual target_ops methods
in the target_ops base class.

At this point no actual targets override target_ops::fileio_stat, so
any attempts to call this function will return ENOSYS error code.

11 months agoX86: Update gas/NEWS for Intel APX.
Cui, Lili [Thu, 18 Jul 2024 07:56:08 +0000 (15:56 +0800)] 
X86: Update gas/NEWS for Intel APX.

gas/ChangeLog:

        * NEWS: Added "APX_F is fully supportted" to gas/NEWS.

11 months agoAutomatic date update in version.in
GDB Administrator [Thu, 18 Jul 2024 00:00:17 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months ago[gdb/testsuite] Fix gdb.arch/arm-pseudo-unwind.exp with unix/mthumb
Tom de Vries [Wed, 17 Jul 2024 15:04:02 +0000 (17:04 +0200)] 
[gdb/testsuite] Fix gdb.arch/arm-pseudo-unwind.exp with unix/mthumb

When running test-case gdb.arch/arm-pseudo-unwind.exp with target board
unix/mthumb, we run into:
...
(gdb) continue^M
Continuing.^M
^M
Program received signal SIGILL, Illegal instruction.^M
0x00400f38 in ?? ()^M
(gdb) FAIL: $exp: continue to breakpoint: continue to callee
...

The test-case attempts to force arm-pseudo-unwind.c to be compiled in arm mode
using additional_flags=-marm, but that's overridden by using target board
unix/mthumb.

This causes function main to be in thumb mode, and consequently function
caller (which is called from main) is is executed as if it's in thumb mode,
while it's actually in arm mode.

Fix this by adding an intermediate function caller_trampoline in
arm-pseudo-unwind.c, and hardcoding it to arm mode using
__attribute__((target("arm"))).

Likewise for test-case gdb.arch/arm-pseudo-unwind-legacy.exp.

Tested on arm-linux.

Approved-By: Luis Machado <luis.machado@arm.com>
11 months agogas: scfi: testsuite: refresh the README
Indu Bhagat [Wed, 17 Jul 2024 06:34:43 +0000 (23:34 -0700)] 
gas: scfi: testsuite: refresh the README

Update some stale text in the README.  Add few more notes to guide
future maintenance of the testsuite.

gas/testsuite/
* gas/scfi/README: Update text.

11 months agoAutomatic date update in version.in
GDB Administrator [Wed, 17 Jul 2024 00:00:18 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agogdb, gdbserver, gdbsupport: use [[noreturn]] instead of ATTRIBUTE_NORETURN
Simon Marchi [Tue, 16 Jul 2024 20:02:12 +0000 (16:02 -0400)] 
gdb, gdbserver, gdbsupport: use [[noreturn]] instead of ATTRIBUTE_NORETURN

C++ 11 has a built-in attribute for this, no need to use a compat macro.

Change-Id: I90e4220d26e8f3949d91761f8a13cd9c37da3875
Reviewed-by: Lancelot Six <lancelot.six@amd.com>
11 months agogdb: fix indentation in remote.c
Simon Marchi [Tue, 16 Jul 2024 18:05:14 +0000 (14:05 -0400)] 
gdb: fix indentation in remote.c

Change-Id: If344acdf703fdd3892f73f75fc891d5473808b79

11 months agogdb: add ATTRIBUTE_NORETURN to remote_unpush_target
Simon Marchi [Tue, 16 Jul 2024 18:03:27 +0000 (14:03 -0400)] 
gdb: add ATTRIBUTE_NORETURN to remote_unpush_target

My IDE (well, clangd) suggested this.  It doesn't hurt to have it.

Change-Id: If6001983c17dbed3dceebac3078c8deb12c04d6b

11 months ago[gdb/testsuite] Simplify gdb.base/complex-parts.exp
Tom de Vries [Tue, 16 Jul 2024 15:22:04 +0000 (17:22 +0200)] 
[gdb/testsuite] Simplify gdb.base/complex-parts.exp

I noticed a lot of escaping in test-case gdb.base/complex-parts.exp.

Make the test-case more readable by using:
- string_to_regexp, and
- {} instead of "".

Tested on x86_64-linux and aarch64-linux.

11 months agoAutomatic date update in version.in
GDB Administrator [Tue, 16 Jul 2024 00:00:18 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agogdb: pass program space to overlay_invalidate_all
Simon Marchi [Mon, 15 Jul 2024 15:29:47 +0000 (15:29 +0000)] 
gdb: pass program space to overlay_invalidate_all

Make the current program space bubble up one level.

Change-Id: I5ac1e3290ad266730465cd60aa3672d45ffa6475

11 months agogdb: pass program space to objfile::make
Simon Marchi [Thu, 16 May 2024 21:30:22 +0000 (17:30 -0400)] 
gdb: pass program space to objfile::make

Make the current program space reference bubble up one level.

Change-Id: Iee8b11c853c76e539c991c4785737c69e6a1925c
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to objfile::objfile
Simon Marchi [Thu, 16 May 2024 21:28:13 +0000 (17:28 -0400)] 
gdb: pass program space to objfile::objfile

Make the current program space reference bubble up one level.

Change-Id: I81e45e89e0cfd87c308f801d49ae811a941348b7
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to entry_point_address
Simon Marchi [Thu, 16 May 2024 21:04:13 +0000 (17:04 -0400)] 
gdb: pass program space to entry_point_address

Make the current program space reference bubble up one level.

Change-Id: Ifc9b8186abaefb10caf99f79ae09e526fa65c882
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to entry_point_address_query
Simon Marchi [Thu, 16 May 2024 21:01:47 +0000 (17:01 -0400)] 
gdb: pass program space to entry_point_address_query

Make the current program space bubble up one level.

Change-Id: Ic3ad0869ca1afe41854f605a6f7eb092fca29ff8
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to objfiles_changed
Simon Marchi [Thu, 16 May 2024 20:59:32 +0000 (16:59 -0400)] 
gdb: pass program space to objfiles_changed

Make the current program space reference bubble up one level.

Change-Id: I9b33c9e0d22c171eb1bb59ce480621b02c7b7bf7
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to get_current_source_symtab_and_line
Simon Marchi [Thu, 16 May 2024 20:50:22 +0000 (16:50 -0400)] 
gdb: pass program space to get_current_source_symtab_and_line

Make the current program space reference bubble up one level.

Change-Id: I6ba6dc4a2cb188720cbb61b84ab5c954aac105c6
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to have_{full,partial}_symbols
Simon Marchi [Thu, 16 May 2024 20:37:06 +0000 (16:37 -0400)] 
gdb: pass program space to have_{full,partial}_symbols

Make the current program space reference bubble up one level.

Change-Id: I19c4fc2ca955f9c828ef426a077b43983865697b
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: bool-ify a few functions in objfiles.{c,h}
Simon Marchi [Thu, 16 May 2024 20:29:47 +0000 (16:29 -0400)] 
gdb: bool-ify a few functions in objfiles.{c,h}

Change return types to bool, and make a few stylistic adjustments.

Change-Id: I784c3c33af0394a77c25064b06eb3e128e69222f
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to clear_current_source_symtab_and_line
Simon Marchi [Thu, 16 May 2024 20:21:23 +0000 (16:21 -0400)] 
gdb: pass program space to clear_current_source_symtab_and_line

Make the current program space reference bubble up one level.

Change-Id: I692554474d17e4f4708fd8ad662bf6c0bb964726
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: make `program_space::free_all_objfiles` use `this`
Simon Marchi [Thu, 16 May 2024 20:13:20 +0000 (16:13 -0400)] 
gdb: make `program_space::free_all_objfiles` use `this`

Use `this` instead of `current_program_space`.  Presumably, the method
wants to check the solibs of "this" program space, not the current
global program space (although they are likely always the same at the
moment).

Change-Id: Iaf0534f36bfd47c04c53ed0657da332bdb8fb906
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to no_shared_libraries
Simon Marchi [Thu, 11 Jul 2024 16:39:35 +0000 (12:39 -0400)] 
gdb: pass program space to no_shared_libraries

Make the current program space reference bubble up one level.  Pass
`current_program_space` everywhere, except in some cases where we can
get the pspace another way, and it's relatively obvious that it's the
same as the current program space.

Change-Id: Id86b79f1e44f92a398f49d137d57457174dfa96d
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: split no_shared_libraries, command vs implementation
Simon Marchi [Thu, 11 Jul 2024 16:38:31 +0000 (12:38 -0400)] 
gdb: split no_shared_libraries, command vs implementation

The `no_shared_libraries` function is currently used to implement the
`nosharedlibrary` command, but it also used internally by other
functions.  This does not make a very good internal API.

Add the `no_shared_libraries_command` function to implement the CLI
command.  Remove the unused parameters from `no_shared_libraries`.

Remove the `from_tty` parameter of `target_pre_inferior`, since it's now
unused.

Change-Id: I4fcba5ee1e0f7d250aab1a7b62b9ea16265fe962
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: pass program space to objfile_purge_solibs
Simon Marchi [Thu, 16 May 2024 19:57:08 +0000 (15:57 -0400)] 
gdb: pass program space to objfile_purge_solibs

Make the current program space reference bubble up one level.

Change-Id: I08cfa77a0351c9602131ed2a294eabb1f1f59a6e
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: use objfile::pspace in objfile::unlink
Simon Marchi [Thu, 16 May 2024 18:04:24 +0000 (14:04 -0400)] 
gdb: use objfile::pspace in objfile::unlink

I think it would make sense to use objfile::pspace instead of the
current program space here.  It reduces the risks of calling this
method with the wrong current program space set.

Change-Id: Id4f3644719f232640c83a1c7f4aa92eaa6af6c5c
Approved-By: Tom Tromey <tom@tromey.com>
Reviewed-By: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
11 months agogdb: remove some trivial uses of current_program_space
Simon Marchi [Mon, 15 Jul 2024 15:02:15 +0000 (15:02 +0000)] 
gdb: remove some trivial uses of current_program_space

It is obvious that pspace is the same as current_program_space in these
cases, due to the set_current_program_space call just above.  The rest
of the functions probably care about the current program space though,
so leave the set_cset_current_program_space calls there.

Change-Id: I3c300decbf2c2fe5f25aa7f697ebcb524432394f

11 months agoFix loading a saved recording
Hannes Domani [Mon, 15 Jul 2024 14:29:36 +0000 (16:29 +0200)] 
Fix loading a saved recording

Currently you get this assertion failure if you try to execute the
inferior after loading a saved recording, when no recording was done
earlier in the same gdb session:
```
$ gdb -q c -ex "record restore test.rec"
Reading symbols from c...
[New LWP 26428]
Core was generated by `/tmp/c'.
Restored records from core file /tmp/test.rec.
(gdb) c
Continuing.
../../gdb/inferior.c:293: internal-error: inferior* find_inferior_pid(process_stratum_target*, int): Assertion `pid != 0' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
```

The change in step-precsave.exp triggers this bug, since now the
recording is loaded in a new gdb session, where
record_full_resume_ptid was never set.

The fix is to simply set record_full_resume_ptid when resuming a loaded
recording.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31971
Approved-By: Guinevere Larsen <blarsen@redhat.com>
11 months agogdb: make objfile::pspace private
Simon Marchi [Mon, 15 Jul 2024 13:54:45 +0000 (13:54 +0000)] 
gdb: make objfile::pspace private

Rename to m_pspace, add getter.  An objfile's pspace never changes, so
no setter is necessary.

Change-Id: If4dfb300cb90dc0fb9776ea704ff92baebb8f626

11 months agoaarch64: Fix --no-apply-dynamic-relocs for RELR
Szabolcs Nagy [Fri, 28 Jun 2024 16:51:24 +0000 (17:51 +0100)] 
aarch64: Fix --no-apply-dynamic-relocs for RELR

The option only makes sense for RELA relative relocs where the
addend is present, not for RELR relative relocs.

Fixes bug 31924.

11 months agoSynchronize config.[sub|guess] with the latest versions from the config project.
Nick Clifton [Mon, 15 Jul 2024 09:22:54 +0000 (10:22 +0100)] 
Synchronize config.[sub|guess] with the latest versions from the config project.

11 months agoAutomatic date update in version.in
GDB Administrator [Mon, 15 Jul 2024 00:00:09 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agohppa: Fix handling of relocations that apply to data
John David Anglin [Sun, 14 Jul 2024 11:22:13 +0000 (07:22 -0400)] 
hppa: Fix handling of relocations that apply to data

Commit d125f9675372b1ae01ceb1893c06ccb27bc7bf22 introduced a bug
in handling relocations for data.  The R_PARISC_DIR32 relocation
operates on 32-bit data and not instructions.  The HOWTO table
needs to be used to determine the format of relocations that apply
to data.  The R_PARISC_SEGBASE relocation is another special case
as it only changes segment base.

This was noticed in Debian cmor package build.

2024-07-14  John David Anglin  <danglin@gcc.gnu.org>

bfd/ChangeLog:

* elf32-hppa.c (final_link_relocate): Use HOWTO table to
determine reload format for relocations that apply to data.

11 months agoAutomatic date update in version.in
GDB Administrator [Sun, 14 Jul 2024 00:00:10 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agoRevert "MIPS: Use N64 by default for mips*64*-*-linux-gnuabi64"
Maciej W. Rozycki [Sat, 13 Jul 2024 05:00:44 +0000 (06:00 +0100)] 
Revert "MIPS: Use N64 by default for mips*64*-*-linux-gnuabi64"

This reverts commit d49f2dd78b08efa4e1ee51f5df5058846c2eb4fa.  It was
applied unapproved.

11 months agoRevert "MIPS/GAS: Omit LI 0 for condition trap"
Maciej W. Rozycki [Sat, 13 Jul 2024 05:00:43 +0000 (06:00 +0100)] 
Revert "MIPS/GAS: Omit LI 0 for condition trap"

This reverts commit bfa257b407270d1c808b31fbd97da779e0fd20d2.  It was
applied unapproved.

11 months agoLoongArch: Fix dwarf3 test cases from XPASS to PASS
Lulu Cai [Thu, 11 Jul 2024 11:00:43 +0000 (19:00 +0800)] 
LoongArch: Fix dwarf3 test cases from XPASS to PASS

In the past, the .align directive generated a label that did not match
the regular expression, and we set it to XFAIL.
But now it matches fine so it becomes XPASS. We fix it with PASS.

11 months agoAutomatic date update in version.in
GDB Administrator [Sat, 13 Jul 2024 00:00:11 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agolibiberty: sync with gcc
Sam James [Sat, 29 Jun 2024 17:11:52 +0000 (18:11 +0100)] 
libiberty: sync with gcc

This imports the following commits from GCC as of r15-1722-g7682d115402743:
ca2f7c84927f libiberty: Invoke D demangler when --format=auto
94792057ad4a Fix up duplicated words mostly in comments, part 1
20e57660e64e libiberty: Fix error return value in pex_unix_exec_child [PR113957].
52ac4c6be866 [libiberty] remove TBAA violation in iterative_hash, improve code-gen
53bb7145135c libiberty: Fix up libiberty_vprintf_buffer_size
65388b28656d c++, demangle: Implement https://github.com/itanium-cxx-abi/cxx-abi/issues/148 non-proposal

11 months agos390: Avoid reloc overflows on undefined weak symbols (cont)
Jens Remus [Fri, 12 Jul 2024 14:53:47 +0000 (16:53 +0200)] 
s390: Avoid reloc overflows on undefined weak symbols (cont)

This complements and reuses logic from Andreas Krebbel's commit
896a639babe2 ("s390: Avoid reloc overflows on undefined weak symbols").

Replace relative long addressing instructions of weak symbols, which
will definitely resolve to zero, with either a load address of 0 or a
a trapping insn.

This prevents the PLT32DBL relocation from overflowing in case the
binary will be loaded at 4GB or more.

bfd/
* elf64-s390.c (elf_s390_relocate_section): Replace
instructions using undefined weak symbols with relative
addressing to avoid relocation overflows.

ld/
* testsuite/ld-s390/s390.exp: Add new test.
* testsuite/ld-s390/weakundef-2.s: New test.
* testsuite/ld-s390/weakundef-2.dd: Likewise.

Reported-by: Alexander Gordeev <agordeev@linux.ibm.com>
Suggested-by: Ilya Leoshkevich <iii@linux.ibm.com>
Suggested-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
11 months agos390: Do not replace brcth referencing undefined weak symbol
Jens Remus [Fri, 12 Jul 2024 14:53:47 +0000 (16:53 +0200)] 
s390: Do not replace brcth referencing undefined weak symbol

Branch Relative on Count High (brcth) is a conditional branch relative
instruction. It is not guaranteed that it only appears within loops
that sooner or later will take the branch. It may very well be used to
check a condition that will prevent the branch from ever being taken.

bfd/
* elf64-s390.c (elf_s390_relocate_section): Do not replace brcth
referencing undefined weak symbol with a trap.

ld/
* testsuite/ld-s390/weakundef-1.s: Update test case accordingly.
* testsuite/ld-s390/weakundef-1.dd: Likewise.

Fixes: 896a639babe2 ("s390: Avoid reloc overflows on undefined weak symbols")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
11 months agoaarch64: Add support for sme2.1 zero instructions.
Srinath Parvathaneni [Mon, 8 Jul 2024 15:36:44 +0000 (16:36 +0100)] 
aarch64: Add support for sme2.1 zero instructions.

This patch adds support for following sme2.1 zero instructions and
the spec is available here [1].

1. ZERO (single-vector).
2. ZERO (double-vector).
3. ZERO (quad-vector).

The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler
for most of the sme and sve instructions. But for few of the sme2.1
zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory.
To address this a bit "F_VG_REQ" is introduced in this patch, on setting
F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept
instruction operand only having VECTOR GROUP symbols.

[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en

11 months agoaarch64: Add support for sme2.1 movaz instructions.
Srinath Parvathaneni [Mon, 8 Jul 2024 15:36:42 +0000 (16:36 +0100)] 
aarch64: Add support for sme2.1 movaz instructions.

This patch adds support for following sme2.1 movaz instructions and
the spec is available here [1].

1. MOVAZ (array to vector, two registers).
2. MOVAZ (array to vector, four registers).
3. MOVAZ (tile to vector, single).

[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en

11 months agoaarch64: Add support for sme2.1 luti2 and luti4 instructions.
Srinath Parvathaneni [Mon, 8 Jul 2024 15:36:40 +0000 (16:36 +0100)] 
aarch64: Add support for sme2.1 luti2 and luti4 instructions.

This patch adds support for following sme2.1 luti2 and luti4 instructions, spec is
available here [1]

1. LUTI2 (two registers) strided.
2. LUTI2 (four registers) strided.
3. LUTI4 (two registers) strided.
4. LUTI4 (four registers) strided.

[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en

11 months agox86: drop unnecessary \() from bundle tests
Jan Beulich [Fri, 12 Jul 2024 10:28:50 +0000 (12:28 +0200)] 
x86: drop unnecessary \() from bundle tests

':' isn't permitted in macro parameter names, hence this separator
construct isn't necessary at the end of labels. Drop its use in such
cases, for being potentially confusing (and hampering readability, even
if only a little).

11 months agox86/APX: remove two inconsistencies
Jan Beulich [Fri, 12 Jul 2024 10:28:03 +0000 (12:28 +0200)] 
x86/APX: remove two inconsistencies

As indicated in earlier discussion, permitting GOTTPOFF uniformly for
all legacy non-SIMD insns while at the same time restricting to just
certain ADD forms when EVEX-encoded is inconsistent. Make promoted insns
"equal" to their legacy original ones. Doing that adjustment prevents
another inconsistency, too: In

data16 neg (%rax)
data16 neg (%r16)
data16 {nf} neg (%rax)

it is not logical why the last one shouldn't be permitted. Bypassing
that check requires other adjustments, though, to actually properly
consume (and then squash) the data size prefix.

While there also add the missing CMP and TEST cases to the test case
being modified.

11 months agox86/APX: correct TEST/CTESTcc with 1st operand being a memory one
Jan Beulich [Fri, 12 Jul 2024 10:27:19 +0000 (12:27 +0200)] 
x86/APX: correct TEST/CTESTcc with 1st operand being a memory one

While they properly inherited D and C, code processing the reversal of
operands wasn't updated accordingly (and "reversed" operands also
weren't tested anywhere).

11 months agoMIPS/GAS: Omit LI 0 for condition trap
YunQiang Su [Wed, 19 Jun 2024 16:52:25 +0000 (00:52 +0800)] 
MIPS/GAS: Omit LI 0 for condition trap

MIPSr6 removes condition trap instructions with imm, so we expand
the instruction like "tne $2,IMM" to
li $at,IMM
tne $2,$at
While if IMM is 0, we can use
tne $2,$zero
only.

11 months agoMIPS: Use N64 by default for mips*64*-*-linux-gnuabi64
YunQiang Su [Fri, 12 Jul 2024 10:18:59 +0000 (18:18 +0800)] 
MIPS: Use N64 by default for mips*64*-*-linux-gnuabi64

the ABI section of the triple explicitly asks for N64,
and in fact GCC also does so.

It can fix the test failure:
  FAIL: libdep test: did not get expected output from the linker
with Debian's mipsisa64r6el-linux-gnuabi64 toolchain.

11 months agoaarch64: disable feature b16b16
Matthieu Longo [Fri, 12 Jul 2024 08:02:08 +0000 (09:02 +0100)] 
aarch64: disable feature b16b16

Feature b16b16 is currently incomplete and requires re-work.

Disable the command line option for b16b16, and mark the associated
tests as XFAIL.

11 months agogprofng: add release notes for 2.43
Vladimir Mezentsev [Wed, 10 Jul 2024 22:57:50 +0000 (15:57 -0700)] 
gprofng: add release notes for 2.43

ChangeLog
2024-07-10  Vladimir Mezentsev  <vladimir.mezentsev@oracle.com>.

* binutils/NEWS (gprofng): Add release notes for 2.43

11 months agoRe: base64: Add support for targets with byte size > octet size.
Alan Modra [Fri, 12 Jul 2024 00:20:46 +0000 (09:50 +0930)] 
Re: base64: Add support for targets with byte size > octet size.

Three extra octets are now expected with the latest change to base64.s.
They happened to be covered by patterns allowing for zero padding at
the end of the section, but we don't want to allow fewer octets than
expected.

PR 31964
* testsuite/gas/all/base64.d: Adjust.

11 months agoAutomatic date update in version.in
GDB Administrator [Fri, 12 Jul 2024 00:00:09 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agobase64: Add support for targets with byte size > octet size.
Nick Clifton [Thu, 11 Jul 2024 11:51:16 +0000 (12:51 +0100)] 
base64: Add support for targets with byte size > octet size.

PR 31964

11 months agogas: don't open-code IS_WHITESPACE() / IS_NEWLINE()
Jan Beulich [Thu, 11 Jul 2024 10:27:18 +0000 (12:27 +0200)] 
gas: don't open-code IS_WHITESPACE() / IS_NEWLINE()

Better be consistent in use of the wrapper macros, which imo also helps
readability.

11 months agogas: multi-byte warning adjustments
Jan Beulich [Thu, 11 Jul 2024 10:26:36 +0000 (12:26 +0200)] 
gas: multi-byte warning adjustments

First input_scrub_next_buffer()'s invocation was wrong, leading to input
only being checked from the last newline till the end of the current
buffer. Correcting the invocation, however, leads to duplicate checking
unless -f (or the #NO_APP equivalent thereof) is in effect. Move the
invocation to input_file_give_next_buffer(), to restrict it accordingly.

Then, when macros contain multi-byte characters, warning about them
again in every expansion isn't useful. Suppress such warnings from
sb_scrub_and_add_sb().

11 months agogas: there's no scrubber state 12
Jan Beulich [Thu, 11 Jul 2024 10:25:26 +0000 (12:25 +0200)] 
gas: there's no scrubber state 12

Apparently (beyond what's [easily] visible in git history) when this was
added there was confusion about scrubber states vs lex[] contents. For
the purposes here LEX_IS_DOUBLEDASH_1ST (which happens to also resolve
to 12) alone is sufficient. "state" is never set to 12, and it being 12
also isn't handled anywhere.

11 months agogdb: add testcase for invalid record display
Kévin Le Gouguec [Thu, 4 Jul 2024 06:45:01 +0000 (08:45 +0200)] 
gdb: add testcase for invalid record display

More of a DWARF-generation non-regression test; fixed on the GCC side
with 2024-06-03 "Implement wrap-around arithmetics in DWARF
expressions" (f3d6d60d2ae).

Approved-By: Tom Tromey <tom@tromey.com>
11 months agoX86: Update gas/NEWS for Intel APX.
Cui, Lili [Thu, 11 Jul 2024 06:35:24 +0000 (14:35 +0800)] 
X86: Update gas/NEWS for Intel APX.

gas/ChangeLog:

        * NEWS: Update gas/NEWS for Intel APX.

11 months agoRISC-V: Add platform property/capability extensions
Tsukasa OI [Wed, 26 Jul 2023 00:05:53 +0000 (00:05 +0000)] 
RISC-V: Add platform property/capability extensions

RISC-V Profiles document defines number of "extensions" that indicate
certain platform properties/capabilities just like 'Zkt' extension from the
RISC-V cryptography extensions.

This commit defines 20 platform property/capability extensions as defined
in the RISC-V Profiles documentation.

The only exception: 'Ssstateen' extension is defined separately because it
defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension.

This is based on the ratified version of RISC-V Profiles:
<https://github.com/riscv/riscv-profiles/releases/tag/v1.0>

[Definition]

"Main memory regions":
    Main memory regions (in contrast to I/O or vacant memory regions) with
    both the cacheability and coherence PMAs.

[New Unprivileged Extensions]

1.  'Ziccif'
    "Main memory regions" support instruction fetch and any instruction
    fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN)
    are atomic.
2.  'Ziccrse'
    "Main memory regions" provide the eventual success guarantee for
    LR/SC sequence (RsrvEventual).
3.  'Ziccamoa'
    "Main memory regions" support all currently-defined AMO operations
    including swap, logical and arithmetic operations (AMOArithmetic).
4.  'Za64rs'
    For LR/SC instructions, reservation sets are contiguous, naturally
    aligned and at most 64-bytes in size.
5.  'Za128rs'
    Likewise, but reservation sets are at most 128-bytes in size.
6.  'Zicclsm'
    Misaligned loads / stores to "main memory regions" are supported.
    Those include both regular scalar and vector accesses but does not
    include AMOs and other specialized forms of memory accesses.
7.  'Zic64b'
    Cache blocks are (exactly) 64-bytes in size and naturally aligned.

[New Privileged Extensions]

1.  'Svbare'
    "satp" mode Bare is supported.
2.  'Svade'
    Page-fault exceptions are raised when a page is accessed when A bit is
    clear, or written when D bit is clear.
3.  'Ssccptr'
    "Main memory regions" support hardware page-table reads.
4.  'Sstvecd'
    "stvec" mode Direct is supported.  When "stvec" mode is Direct,
    "stvec.BASE" is capable of holding any valid 4-byte aligned address.
5.  'Sstvala'
    "stval" is always written with a nonzero value whenever possible as
    specified in the Privileged Architecture documentation
    (version 20211203: see section 4.1.9).
6.  'Sscounterenw'
    For any "hpmcounter" that is not read-only zero, the corresponding bit
    in "scounteren" is writable.
7.  'Ssu64xl'
    "sstatus.UXL" is capable of holding the value 0b10
    (UXLEN==64 is supported).
8.  'Shcounterenw'
    Similar to 'Sscounterenw' but the same rule applies to "hcounteren".
9.  'Shvstvala'
    Similar to 'Sstvala' but the same rule applies to "vstval".
10. 'Shtvala'
    "htval" is written with the faulting guest physical address as long as
    permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala').
11. 'Shvstvecd'
    Similar to 'Sstvecd' but the same rule applies to "vstvec".
12. 'Shvsatpa'
    All translation modes supported in "satp" are also supported in "vsatp".
13. 'Shgatpa'
    For each supported virtual memory scheme SvNN supported in "satp", the
    corresponding "hgatp" SvNNx4 mode is supported.  The "hgatp" mode Bare
    is also supported.

[Implications]

(Due to reservation set size constraints)
-   'Za64rs' -> 'Za128rs'

(Due to the fact that a privileged "extension" directly refers a CSR)
-   'Svbare'       -> 'Zicsr'
-   'Sstvecd'      -> 'Zicsr'
-   'Sstvala'      -> 'Zicsr'
-   'Sscounterenw' -> 'Zicsr'
-   'Ssu64xl'      -> 'Zicsr'

(Due to the fact that a privileged "extension" indirectly depends on CSRs)
-   'Svade' -> 'Zicsr'

(Due to the fact that a privileged "extension" is a hypervisor property)
-   'Shcounterenw' -> 'H'
-   'Shvstvala'    -> 'H'
-   'Shtvala'      -> 'H'
-   'Shvstvecd'    -> 'H'
-   'Shvsatpa'     -> 'H'
-   'Shgatpa'      -> 'H'

bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Updated for property
and capability extensions.
(riscv_supported_std_z_ext): Added zic64b, ziccamoa, ziccif, zicclsm,
ziccrse, za64rs and za128rs extensions.
(riscv_supported_std_s_ext): Added shcounterenw, shgatpa, shtvala,
shvsatpa, shvstvala, shvstvecd, ssccptr, sscounterenw, sstvala,
sstvecd, ssu64xlm svade and svbare extensions.
gas/
* testsuite/gas/riscv/imply.d: Updated for property and capability
extensions.
* testsuite/gas/riscv/imply.s: Likewise.
* testsuite/gas/riscv/march-help.l: Likewse.

11 months agoRe: Add support for a .base64 pseudo-op to gas
Alan Modra [Thu, 11 Jul 2024 01:38:50 +0000 (11:08 +0930)] 
Re: Add support for a .base64 pseudo-op to gas

Fixes a failure on rx-elf where the standard data section isn't .data.
run_dump_test has machinery to translate .data in both options and
expected results for objdump, but not for readelf -x.

PR 31964
* testsuite/gas/all/base64.d: Dump .data with objdump.  Run on
all targets.

11 months agoLoongArch: Not alloc dynamic relocs if symbol is absolute
Jinyang He [Mon, 8 Jul 2024 03:27:52 +0000 (11:27 +0800)] 
LoongArch: Not alloc dynamic relocs if symbol is absolute

The absolute symbol should be resolved to const when link to dso or exe.
Alloc dynamic relocs will cause extra space and R_LARCH_NONE finally.

11 months agoAutomatic date update in version.in
GDB Administrator [Thu, 11 Jul 2024 00:00:15 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agox86-64: Skip -z mark-plt tests on MUSL
H.J. Lu [Wed, 10 Jul 2024 23:46:21 +0000 (16:46 -0700)] 
x86-64: Skip -z mark-plt tests on MUSL

Skip -z mark-plt tests, which are specific to glibc, on MUSL.

PR ld/31970
* ld/testsuite/ld-x86-64/x86-64.exp: Skip -z mark-plt tests on
MUSL.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
11 months agoRISC-V:[gprofng] Minimal support gprofng for riscv.
Yixuan Chen [Thu, 4 Jul 2024 09:16:59 +0000 (17:16 +0800)] 
RISC-V:[gprofng] Minimal support gprofng for riscv.

ChangeLog: Add target riscv to --enable-gprofng.

2024-07-04  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * configure: Add riscv.
        * configure.ac: Add riscv.

gprofng/ChangeLog: Minimal support gprofng for riscv.

2024-07-04  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
        (defined): Add riscv.
        * gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
        * gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
        (defined): Add riscv.
        (ARCH_RISCV): Add riscv.
        * gprofng/common/hwc_cpus.h: Add RISC-V vendor.
        * gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
        * gprofng/configure: Add riscv.
        * gprofng/configure.ac: Add riscv.
        * gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
        (CONTEXT_PC): Add RISC-V register.
        (CONTEXT_FP): Add RISC-V register.
        (CONTEXT_SP): Add RISC-V register.
        (SETFUNCTIONCONTEXT):
        * gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
        * gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
        * gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
        (GET_PC): Add RISC-V register.
        (GET_SP): Add RISC-V register.
        (GET_FP): Add RISC-V register.
        (FILL_CONTEXT):
        * gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
        * gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
        * gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
        * gprofng/src/checks.cc (ARCH): Add RISC-V.
        * gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
        (read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
        * gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.

11 months agoAdd support for a .base64 pseudo-op to gas
Nick Clifton [Wed, 10 Jul 2024 14:01:39 +0000 (15:01 +0100)] 
Add support for a .base64 pseudo-op to gas

  PR 31964

11 months agolibsframe: remove runstatedir in Makefile.in
Clément Chigot [Wed, 10 Jul 2024 08:24:45 +0000 (10:24 +0200)] 
libsframe: remove runstatedir in Makefile.in

The regeneration was made with Ubuntu automake which has this runstatedir
additional variable, compared to the usual automake.

11 months agolibsframe: accept --target configure option
Clément Chigot [Mon, 8 Jul 2024 08:55:48 +0000 (10:55 +0200)] 
libsframe: accept --target configure option

Libsframe was missing AC_CANONICAL_TARGET, meaning that --target was
ignored. This could prevent libsframe.a to be installed in some cases,
the host fetching its canonical value while the target isn't. Both
having a different value, INSTALL_LIBBFD would be false.

11 months agoAutomatic date update in version.in
GDB Administrator [Wed, 10 Jul 2024 00:00:36 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agoelf: Add glibc version dependency only if needed
H.J. Lu [Tue, 9 Jul 2024 08:48:54 +0000 (01:48 -0700)] 
elf: Add glibc version dependency only if needed

There is no need to add a needed glibc version if the glibc base version
includes the needed glibc version.

PR ld/31966
* elflink.c (elf_link_add_glibc_verneed): Add glibc_minor_base.
Skip if the glibc base version includes the needed glibc version.
(_bfd_elf_link_add_glibc_version_dependency): Initialize
glibc_minor_base to INT_MAX and pass it to
elf_link_add_glibc_verneed.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
11 months agogprofng: add hardware counters for Intel Ice Lake processor
Vladimir Mezentsev [Mon, 8 Jul 2024 02:44:46 +0000 (19:44 -0700)] 
gprofng: add hardware counters for Intel Ice Lake processor

gprofng/ChangeLog
2024-07-07  Vladimir Mezentsev  <vladimir.mezentsev@oracle.com>.

* common/hwc_cpus.h: New constant for Intel Ice Lake processor.
* common/hwcdrv.c: Add a new argument to hwcfuncs_get_x86_eventsel.
Set config1 in perf_event_attr. Remove the use of memset.
* common/core_pcbe.c (core_pcbe_get_eventnum): Return 0.
* common/hwcentry.h: Add config1.
* src/collctrl.cc (Coll_Ctrl::build_data_desc):Set config1.
* common/hwcfuncs.c (process_data_descriptor): Set config1.
* common/hwctable.c: Add the hwc table for Intel Ice Lake processor.
* src/hwc_intel_icelake.h: New file.

11 months agodoc: sframe: add appendix for generating stack traces
Indu Bhagat [Wed, 26 Jun 2024 19:43:51 +0000 (12:43 -0700)] 
doc: sframe: add appendix for generating stack traces

Add an appendix to provide a rough outline to show how to generate stack
traces using the SFrame format.  Such content should hopefully aid the
reader assimmilate the information in the specification.

libsframe/
* doc/sframe-spec.texi: Add new appendix.

11 months agoinclude: sframe: update code comments around SFrame FRE stack offsets
Indu Bhagat [Fri, 19 Apr 2024 23:48:17 +0000 (16:48 -0700)] 
include: sframe: update code comments around SFrame FRE stack offsets

This also amends the incorrect comment:
    offset3 (intrepreted as FP = CFA + offset2)

If RA tracking is enabled,  the offset to recover FP is at the third
index.  The SFrame format (V2) has assumption that if FP is saved on
stack, RA must have been saved as well.  This is true for the currently
supported arch Aarch64.  For AMD64, RA tracking per SFrame FRE is not
necessary.

In future, when extending support for more architectures, this will
likely need to be revisited.

include/
* sframe.h: Make the comments clearer by enumerating what
happens per-ABI.

11 months agodoc: sframe: segregate the ABI/arch-specific components
Indu Bhagat [Thu, 23 May 2024 21:18:23 +0000 (14:18 -0700)] 
doc: sframe: segregate the ABI/arch-specific components

The recipe to interpret the SFrame FRE stack offsets is
ABI/arch-specific.

Although, there is other information in the specification that is
ABI-specific (like pauth_key usage in AArch64), those pieces of
information are now assimmilated in the SFrame specification in a way
that it is fairly difficult to carve then out into a ABI/arch-specific
section without confusing the readers.

For future though, the specification must strive to keep the generic
parts and ABI/arch-specific parts clearly laid out in separate sections.

libsframe/
* doc/sframe-spec.texi: Reorder and adapt the contents.

11 months agoLTO: Properly check wrapper symbol
H.J. Lu [Tue, 9 Jul 2024 08:30:19 +0000 (01:30 -0700)] 
LTO: Properly check wrapper symbol

Add wrapper_symbol to bfd_link_hash_entry and set it to true for wrapper
symbol. Set wrap_status to wrapper if wrapper_symbol is true in LTO.

Note: Calling unwrap_hash_lookup to check for the wrapper symbol works
only when there is a definition for the wrapped symbol since references
to the wrapped symbol have been redirected to the wrapper symbol.

bfd/

PR ld/31956
* linker.c (bfd_wrapped_link_hash_lookup): Set wrapper_symbol
for wrapper symbol.

include/

PR ld/31956
* bfdlink.h (bfd_link_hash_entry): Add wrapper_symbol.

ld/

PR ld/31956
* plugin.c (get_symbols): Set wrap_status to wrapper if
wrapper_symbol is set.
* testsuite/ld-plugin/lto.exp: Run PR ld/31956 tests.
* testsuite/ld-plugin/pr31956a.c: New file.
* testsuite/ld-plugin/pr31956b.c: Likewise.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
11 months agoAutomatic date update in version.in
GDB Administrator [Tue, 9 Jul 2024 00:00:08 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agoaarch64: Add support for sve2p1 pmov instruction.
srinath [Mon, 8 Jul 2024 16:44:33 +0000 (17:44 +0100)] 
aarch64: Add support for sve2p1 pmov instruction.

This patch adds support for followign SVE2p1 instruction, spec is available here [1].

1. PMOV (to vector)
2. PMOV (to predicate)

Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.

AARCH64_OPND_SVE_Zn0_INDEX,      /* Zn[index], bits [9:5].  */
AARCH64_OPND_SVE_Zn1_17_INDEX,    /* Zn[index], bits [9:5,17].  */
AARCH64_OPND_SVE_Zn2_18_INDEX,    /* Zn[index], bits [9:5,18:17].  */
AARCH64_OPND_SVE_Zn3_22_INDEX,    /* Zn[index], bits [9:5,18:17,22].  */
AARCH64_OPND_SVE_Zd0_INDEX,      /* Zn[index], bits [4:0].  */
AARCH64_OPND_SVE_Zd1_17_INDEX,    /* Zn[index], bits [4:0,17].  */
AARCH64_OPND_SVE_Zd2_18_INDEX,    /* Zn[index], bits [4:0,18:17].  */
AARCH64_OPND_SVE_Zd3_22_INDEX,    /* Zn[index], bits [4:0,18:17,22].  */

Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".

As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
             PMOV <Pn>.D, <Zd>{[<imm>]}

Example1:
Assembly: pmov z5[0], p6.d
Disassembly: pmov z5, p6.d

        Assembly: pmov z5, p6.d
        Disassembly: pmov z5, p6.d

Example2:
Assembly: pmov p4.b, z5[0]
Disassembly: pmov p4.b, z5

        Assembly: pmov p4.b, z5
        Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

11 months agoaarch64: Add support for sve2p1 tbxq instruction.
Srinath Parvathaneni [Mon, 8 Jul 2024 16:44:29 +0000 (17:44 +0100)] 
aarch64: Add support for sve2p1 tbxq instruction.

This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

11 months agoaarch64: Add support for sve2p1 zipq[1-2] instructions.
Srinath Parvathaneni [Mon, 8 Jul 2024 16:44:27 +0000 (17:44 +0100)] 
aarch64: Add support for sve2p1 zipq[1-2] instructions.

This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is
available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

11 months agoaarch64: Add support for sve2p1 uzpq[1-2] instructions.
Srinath Parvathaneni [Mon, 8 Jul 2024 16:44:26 +0000 (17:44 +0100)] 
aarch64: Add support for sve2p1 uzpq[1-2] instructions.

This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is
available here [1]
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

11 months agoaarch64: Add support for sve2p1 tblq instruction.
Srinath Parvathaneni [Mon, 8 Jul 2024 16:44:24 +0000 (17:44 +0100)] 
aarch64: Add support for sve2p1 tblq instruction.

This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

11 months agoaarch64: Add support for sve2p1 orqv instruction.
Srinath Parvathaneni [Mon, 8 Jul 2024 16:44:20 +0000 (17:44 +0100)] 
aarch64: Add support for sve2p1 orqv instruction.

This patch adds support for SVE2p1 "orqv" instruction, spec available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

11 months agoAutomatic date update in version.in
GDB Administrator [Mon, 8 Jul 2024 00:00:12 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agoAutomatic date update in version.in
GDB Administrator [Sun, 7 Jul 2024 00:00:09 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agoRe: LoongArch: Add DT_RELR support
Alan Modra [Sat, 6 Jul 2024 02:00:38 +0000 (11:30 +0930)] 
Re: LoongArch: Add DT_RELR support

Fix commit d89ecf33ab testsuite breakage.

* testsuite/lib/binutils-common.exp (supports_dt_relr): Correct.

11 months agoobjcopy bfd_map_over_sections and global status
Alan Modra [Fri, 5 Jul 2024 13:11:49 +0000 (22:41 +0930)] 
objcopy bfd_map_over_sections and global status

This patch started life as a relatively simple change to fix some
unimportant objcopy memory leaks, but expanded into a larger patch
when I was annoyed by the awkwardness of passing data when using
bfd_map_over_sections.  A simple loop over sections is much more
convenient, and we really don't need the abstraction layer.  Sections
in a list isn't going to disappear any time soon.

The patch also removes use of the global "status" variable by all but
the top-level functions called from main.

* objcopy.c (filter_symbols): Return success as a bool.  Pass
symcount as a pointer, updated on return.
(merge_gnu_build_notes): Similarly return a bool and add newsize
param with updated smaller section size.
(setup_bfd_headers): Return bool success rather than setting
"status" on failure.
(setup_section): Likewise.
(copy_relocations_in_section, copy_section): Likewise, and adjust
params.
(mark_symbols_used_in_relocations): Likewise, and free memory
on failure path.  Don't call bfd_fatal.
(get_sections): Delete function.
(copy_object): Don't use bfd_map_over_sections, instead use a
loop allowing easy detection of failure status.  Free memory on
error paths.
(copy_archive): Return bool success rather than setting "status"
on failure.
(copy_file): Set "status" here.
* testsuite/binutils-all/strip-13.d: Adjust to suit.

11 months agoAutomatic date update in version.in
GDB Administrator [Sat, 6 Jul 2024 00:00:07 +0000 (00:00 +0000)] 
Automatic date update in version.in

11 months agoaarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)
Matthieu Longo [Wed, 3 Jul 2024 17:37:45 +0000 (18:37 +0100)] 
aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.

11 months agoaarch64: add STEP2 feature and its associated registers
Matthieu Longo [Wed, 3 Jul 2024 17:36:26 +0000 (18:36 +0100)] 
aarch64: add STEP2 feature and its associated registers

AArch64 defines new registers for the feature step2 (Enhanced Software Step
Extension). step2 is an Armv9.5-A feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.

11 months agoaarch64: add SPMU2 feature and its associated registers
Matthieu Longo [Wed, 19 Jun 2024 19:10:22 +0000 (20:10 +0100)] 
aarch64: add SPMU2 feature and its associated registers

AArch64 defines new registers for the feature spmu2 (System Performance
Monitors Extension version 2). spmu2 is an Armv9.5-A feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.

11 months agoaarch64: add E3DSE feature and its associated registers
Matthieu Longo [Wed, 19 Jun 2024 19:08:17 +0000 (20:08 +0100)] 
aarch64: add E3DSE feature and its associated registers

AArch64 defines new registers for the feature e3dse (Delegated SError
exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A
feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.

11 months agox86-64: Fix support for APX NF TLS IE with 2 operands
Lingling Kong [Thu, 4 Jul 2024 08:45:46 +0000 (16:45 +0800)] 
x86-64: Fix support for APX NF TLS IE with 2 operands

Added the restriction in assemble for APX TLS IE that the destination
can only be a register.

gas/

      * config/tc-i386.c (md_assemble): Added stricter restrictions
      for APX TLS IE.

11 months agoRISC-V: avoid use of match_opcode() in riscv_insn_types[]
Jan Beulich [Fri, 5 Jul 2024 06:39:28 +0000 (08:39 +0200)] 
RISC-V: avoid use of match_opcode() in riscv_insn_types[]

As of 27b33966b18e ("RISC-V: disallow x0 with certain macro-insns") the
.match_func field may be NULL for entries used for assembly only, which
is the case for the entire table. With .match and .mask both zero the
function would only ever succeed anyway. Save almost a hundred base
relocations in the final executable by using NULL instead.

11 months agoaarch64: fix build with old glibc
Jan Beulich [Fri, 5 Jul 2024 06:38:39 +0000 (08:38 +0200)] 
aarch64: fix build with old glibc

As was pointed out several times before, old glibc declares index(),
resulting in warnings from -Wshadow, in turn failing the build due to
-Werror.

11 months agoLoongArch: Add DT_RELR tests
Xi Ruoyao [Sun, 30 Jun 2024 07:18:25 +0000 (15:18 +0800)] 
LoongArch: Add DT_RELR tests

Most tests are ported from AArch64.

The relr-addend test is added to make sure the addend (link-time address)
is correctly written into the relocated section.  Doing so is not
strictly needed for RELA, but strictly needed for RELR).

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
11 months agoLoongArch: Add DT_RELR support
Xi Ruoyao [Sun, 30 Jun 2024 07:18:24 +0000 (15:18 +0800)] 
LoongArch: Add DT_RELR support

The logic is same as a71d87680110 ("aarch64: Add DT_RELR support").

As LoongArch does not have -z dynamic-undefined-weak, we don't need to
consider UNDEFWEAK_NO_DYNAMIC_RELOC.

The linker relaxation adds another layer of complexity.  When we delete
bytes in a section during relaxation, we need to fix up the offset in
the to-be-packed relative relocations against this section.

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
11 months agoLoongArch: Make protected function symbols local for -shared
Xi Ruoyao [Sun, 30 Jun 2024 07:18:23 +0000 (15:18 +0800)] 
LoongArch: Make protected function symbols local for -shared

On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols
as preemptible.  See the comment above LARCH_REF_LOCAL for detailed
explanation.

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
11 months agoLoongArch: Fix bad reloc with mixed visibility ifunc symbols in shared libraries
Xi Ruoyao [Sun, 30 Jun 2024 07:18:22 +0000 (15:18 +0800)] 
LoongArch: Fix bad reloc with mixed visibility ifunc symbols in shared libraries

With a simple test case:

    .globl  ifunc
    .globl  ifunc_hidden
    .hidden ifunc_hidden
    .type   ifunc, %gnu_indirect_function
    .type   ifunc_hidden, %gnu_indirect_function

    .text
    .align  2
    ifunc:  ret
    ifunc_hidden: ret

    test:
      bl ifunc
      bl ifunc_hidden

"ld -shared" produces a shared object with one R_LARCH_NONE (instead of
R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc".
It's because the indices in .plt and .rela.plt mismatches for
STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a
STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of
loongarch_elf_finish_dynamic_symbol.  Fix the issue by reordering .plt
so the indices no longer mismatch.

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
11 months agoLoongArch: Reject R_LARCH_32 from becoming a runtime reloc in ELFCLASS64
Xi Ruoyao [Sun, 30 Jun 2024 07:18:21 +0000 (15:18 +0800)] 
LoongArch: Reject R_LARCH_32 from becoming a runtime reloc in ELFCLASS64

We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64:

    $ cat t.s
    .data
    x:
        .4byte x
.4byte 0xdeadbeef
    $ as/as-new t.s -o t.o
    $ ld/ld-new -shared t.o
    $ objdump -R
    a.out:     file format elf64-loongarch

    DYNAMIC RELOCATION RECORDS
    OFFSET           TYPE              VALUE
    00000000000001a8 R_LARCH_RELATIVE  *ABS*+0x00000000000001a8

But this is just wrong: at runtime the dynamic linker will run
*(uintptr *)&x += load_address, clobbering the next 4 bytes of data
("0xdeadbeef" in the example).

If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected
by the Glibc dynamic linker anyway.  And it does not make too much sense
to modify Glibc to support it.  So we can just reject it like x86_64:

    relocation R_X86_64_32 against `.data' can not be used when making a
    shared object; recompile with -fPIC

or RISC-V:

    relocation R_RISCV_32 against non-absolute symbol `a local symbol'
    can not be used in RV64 when making a shared object

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
11 months agox86: Correct position of ".s" for CCMPcc in disassembler
Cui, Lili [Fri, 5 Jul 2024 01:55:41 +0000 (09:55 +0800)] 
x86: Correct position of ".s" for CCMPcc in disassembler

Added new macro %SW to CCMPcc to print ".s" after the mnemonic.

Before:
ccmpbl {dfv=}.s %edx,%eax

After:
ccmpbl.s {dfv=} %edx,%eax

gas/ChangeLog:

        * testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc.
        * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.

opcodes/ChangeLog:

        * i386-dis-evex.h: Added %SW for CCMPcc swap operands.
        * i386-dis.c (struct dis386): Added %SW.
        (putop): Handle %SW.