[AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
Andre Vieira [Tue, 21 May 2019 15:27:28 +0000 (16:27 +0100)]
[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M Baseline
gas/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backport from mainline
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW
replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
Tamar Christina [Tue, 21 May 2019 10:03:45 +0000 (11:03 +0100)]
AArch64: Add SVE DWARF registers
The SVE DRAWF register names are missing from binutils, this may cause objdump
and readelf to ignore certain DRAWF output as the registers are unknown (most
notably CIEs).
This patch adds the registers in accordance to the "DWARF for ARM(r) 64-bit
Architecture (AARch64) with SVE support" documentation [1].
* dwarf.c (dwarf_regnames_aarch64): Add SVE registers.
* testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test.
* testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test.
Alan Modra [Fri, 17 May 2019 09:39:42 +0000 (19:09 +0930)]
PR24567, assertion failure in ldlang.c:6868 when compiling with -flto
As the existing comment said: "a common ought to be overridden by a
def in a -flto object". This patch makes the code actually do that,
rather than allowing a normal object file common to override a -flto
defined symbol.
PR 24567
* plugin.c (plugin_notice): Do not let a common symbol override
a non-common definition in IR.
Tamar Christina [Thu, 11 Apr 2019 10:27:28 +0000 (11:27 +0100)]
AArch64: When DF_BIND_NOW don't use TLSDESC GOT value.
When using DF_BIND_NOW on AArch64 we don't reserve the GOT slot for a TLSDESC,
but we still emitted DT_TLSDESC_GOT and DT_TLSDESC_PLT. This caused random
memory corruption as the "special" value of (bfd_vma)-1 would be set for
dt_tlsdesc_got.
Since we don't have a value of dt_tlsdesc_got I also don't emit DT_TLSDESC_PLT
now becuase it would point to an incomplete PLT. To be able to write the PLT
entry DT_TLSDESC_GOT is needed and since we don't have one we can't write the
PLT entry either.
It is my understanding that GLIBC doesn't need these two entries when not lazy
loading. Conversely AArch32 does not reserve neither the GOT not the PLT slot
when doing DF_BIND_NOW.
AArch32 does not need these checks because these values are initialized to 0
and so the if (...) checks don't pass, but on AArch64 these are initialized
to (bfd_vma)-1 and thus we need some extra checks.
bfd/ChangeLog:
PR ld/24302
* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Don't emit
DT_TLSDESC_GOT and DT_TLSDESC_PLT when DF_BIND_NOW.
(elfNN_aarch64_finish_dynamic_sections): Don't write PLT if DF_BIND_NOW.
ld/ChangeLog:
PR ld/24302
* testsuite/ld-aarch64/aarch64-elf.exp: Add new test.
* testsuite/ld-aarch64/tls-relax-gdesc-le-now.d: New test.
H.J. Lu [Wed, 17 Apr 2019 16:08:46 +0000 (09:08 -0700)]
x86: Also check x86 linker_def for non-shared definition
Since elf_x86_linker_defined sets linker_def in elf_x86_link_hash_entry
for linker defined symbols, SYMBOL_DEFINED_NON_SHARED_P should also check
linker_def in elf_x86_link_hash_entry.
bfd/
PR ld/24458
* elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): Also check x86
linker_def.
Sudakshina Das [Thu, 11 Apr 2019 09:19:37 +0000 (10:19 +0100)]
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
Sudakshina Das [Thu, 11 Apr 2019 09:13:23 +0000 (10:13 +0100)]
[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction
This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
The instructions are as follows:
LDGM Xt, [<Xn|SP>]
STGM Xt, [<Xn|SP>]
*** gas/ChangeLog ***
2019-04-16 Sudakshina Das <sudi.das@arm.com>
Backported from mainline
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-16 Sudakshina Das <sudi.das@arm.com>
Backported from mainline
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
projects / thirdparty / binutils-gdb.git / log
