Michal Simek [Thu, 19 Aug 2021 09:09:37 +0000 (11:09 +0200)]
Makefile: Align fit-dtb.blob and u-boot.itb by 64bits
Enabling MULTI_DTB_FIT and DTB_RESELECT can end up with multi DTBs in FIT
image placed and aligned only by 32bits (4bytes). Based on device tree
specification:
"Specifically, the memory reservation block shall be aligned to an 8-byte boundary
and the structure block to a 4-byte boundary."
is 64bit (8bytes) alignment required. That's why make sure that
fit-dtb.blob and u-boot.itb as our primary target images for Xilinx ZynqMP
are all 64bit aligned.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 11 Aug 2021 12:23:54 +0000 (14:23 +0200)]
xilinx: common: Enabling generic function for DT reselection
U-Boot support board detection at run time and based on it change DT.
This feature is implemented for SOM Kria platforms which contain two
eeproms which contain information about SOM module and CC (Carrier card).
Full U-Boot starts with minimal DT file defined by
CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image.
It is using default setup of board_name variable initializaed to
DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option.
When DTB_RESELECT is enabled board_detection() is called. Keep it your mind
that this code is called before relocation. board_detection() is calling
xilinx_read_eeprom() which fills board_info (xilinx_board_description)
structure which are parsed in board_name_decode().
Based on DT configuration and amount of nvmemX aliases name of the board is
composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev"
<board_revision> "-" <cc_name> "-rev" <cc_revision>.
If CC is not present or more are available it keeps going.
When board name is composed and returned from board_name_decode() it is
assigned to board_name variable which is used by
board_fit_config_name_match() which is called via fdtdec_setup() when it
goes over config options in multi dtb FIT image.
From practical point of view multi DTB image is key point here which has to
contain configs for detected combinations. Unfortunately as of now they
have to be full DTBs and DTBOs are not supported.
needs to be squashed together with:
fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \
arch/arm/dts/zynqmp-cc.dtbo
and only one dtb is in fit:
config_X {
description = "zynqmp-board-cc";
fdt = "board-cc";
};
For creating multi DTBs fit image use mkimage -E, e.g.:
mkimage -E -f all.its all.dtb
When DTB_RESELECT is enabled xilinx_read_eeprom() is called before
relocation and it uses calloc for getting a buffer. Because this is dynamic
memory it is not relocated that's why xilinx_read_eeprom() is called again
as the part of board_init(). This second read with calloc buffer placed in
proper position board_late_init_xilinx() can setup u-boot variables as
before.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Jul 2021 07:59:59 +0000 (09:59 +0200)]
xilinx: Add support for generic board detection
Add support for changing DT at run time. It is done via board_detection()
which returns platform_id and platform_version which can be used via
board_name_decode() to compose board_local_name string which corresponds
with DT which is should be used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Aug 2021 10:30:36 +0000 (12:30 +0200)]
xilinx: common: Change board_info[] handling
Origin code was allocating only pointers to struct xilinx_board_description
and there was separate allocation for structure self and freeing in case of
failure.
The code is directly allocating space for all structures by one calloc to
simlify logic.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Jul 2021 07:55:59 +0000 (09:55 +0200)]
xilinx: Use variable for passing board_name
Use variable which points to DEVICE_TREE by default. The reason for this
change is to enable DTB_RESELECT and MULTI_DTB_FIT where board detection
can be used for change DTB at run time. That's why there must be reference
in board_fit_config_name_match() via variable instead of hardcoding it
which is sufficient for that use case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Aug 2021 09:03:49 +0000 (11:03 +0200)]
xilinx: fru: Replace spaces with \0 in detected name
FRU spec expected \0 for unused symbols but unfortunately a lot of boards
are using spaces instead of \0. That's why after saving it to desc->name
name is checked again and all spaces are converted to \0. This will ensure
that names can be used for string manipulations like concatenation.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 12 Jul 2021 09:14:41 +0000 (11:14 +0200)]
arm64: zynqmp: Create description for generic SC (vpk120-revB)
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 16 Aug 2021 08:51:53 +0000 (10:51 +0200)]
arm64: versal: Add support for vpk120-revB
RevB has different SD level shifter compare to revA. From Versal
perspective description revB should be similar to revA but there are
expected changes in i2c infrastructure which is not described from Versal
point of view yet. Adding revB description as placeholder for other changes
which may come.
From Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
"Input Tap delays for New level shifter(NXP/DIODE) are different from
legacy level shifter tap values.
This patch adds tap delay values for SD3.0 new level shifter.
Default driver supports tap delay values for legacy level shifter
and with this patch mmc driver overwrite them with the new tap values."
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Mon, 16 Aug 2021 06:42:28 +0000 (00:42 -0600)]
mtd: spi-nor: Fix write protection error with 1-byte length
Incase of write operation at offset 0 and with data length 1, we are
observing write protection error.
sf write 0x400000 0 1
device 0 offset 0x0, size 0x1
offset 0x0 is protected and cannot be written
SF: 1 bytes @ 0x0 Written: ERROR -22
This is happening due to return of incorrect status of locked sectors
due to shifting of length in dual parallel connection.
Resolve this issue by avoiding data shift when data length is 1.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
T Karthik Reddy [Fri, 13 Aug 2021 06:35:36 +0000 (00:35 -0600)]
mtd: spi-nor: Switch micron octal flash to dtr
Add support to switch micron octal flash to ddr mode by
setting 0xe7 to flash configuration register.
Add octal_ddr_enable() to spi-nor structure to switch to
octal dtr mode.
SPI_XFER_SET_DDR flag is set to spi_slave flags to specify
the ospi driver to enable ospi dtr.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
T Karthik Reddy [Fri, 13 Aug 2021 06:35:35 +0000 (00:35 -0600)]
mtd: spi-nor: Add support for 8_8_8 protocol
Use 8_8_8 protocol parameter setting for read & pp operations.
Remove READ_8_8_8 & PP_8_8_8 HWCAPS from ignore masks to use
8_8_8 protocol. Also use read & pp hwcaps mask(which enables
all the caps) instead of using individual hwcaps to set hardware
capability. Set read 8_8_8 proto setting when flash flags set with
SPI_NOR_OCTAL_DTR_READ flag.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
mmc: zynq_sdhci: Fix SPL flow issues in mmc driver
Address couple of review comments which are already fixed in mainline.
SPL flow needs zynqmp_mmio way to set tapdelay's. Keep xilinx_pm_request
calls for regular u-boot and use zynqmp_mmio calls for SPL flow and mini
u-boot.
Change Macro's to use BIT() and GENMASK() wherever applicable.
Add WORKAROUND for the Versal card detect stable issue in the comment,
and return -ETIMEDOUT in place of -EIO if the card is not stable.
Print error when set_delay() function returns error.
T Karthik Reddy [Tue, 10 Aug 2021 12:50:19 +0000 (06:50 -0600)]
soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lists.denx.de/pipermail/u-boot/2021-August/457642.html
State: waiting
T Karthik Reddy [Tue, 10 Aug 2021 12:50:18 +0000 (06:50 -0600)]
soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lists.denx.de/pipermail/u-boot/2021-August/457642.html
State: waiting
Michal Simek [Fri, 6 Aug 2021 12:09:32 +0000 (14:09 +0200)]
xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.
Here is what it is happening.
Origin DT.
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
Michal Simek [Thu, 5 Aug 2021 13:50:29 +0000 (15:50 +0200)]
arm64: versal: Do not enable SD HS mode for vck190/vmk180
Current SD level shifter is EOL and needs to be replaced by another part.
Boards with it are going to production soon without any infrastructure for
recongition if this is old/new board. Till this is done do not use HS mode
and limit maximum frequence till 19MHz.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 30 Jul 2021 05:59:29 +0000 (07:59 +0200)]
firmware: xilinx: Use explicit values for all enum values
Based on discussion at
https://lore.kernel.org/r/20200318125003.GA2727094@kroah.com we got
recommendation to use explicit values for all enum values.
The patch is following this recommendation.
mmc: zynq_sdhci: Replace mmc->dev->seq with deviceid
It is incorrect to use mmc->dev->seq to identify SD0 or SD1.
We are already reading "device_id" from DT to identify whether it is SD0
or SD1. It is stored in priv->deviceid.
Replace mmc->dev->seq with priv->deviceid and get node_id as per that.
mtd: spi-nor: Add support for Winbond w25h02jv flash
Add support for Winbond w25h02jv flash with 64KBytes
sector size. This flash has 4-dies of 64MBytes each.
Set SPI_NOR_MULTI_DIE flag as this flash needs split reads.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
spi: mtd: Use split reads if multi-die flag is set
Some flash devices have multiple dies in it & has die cross over
issue. When SPI_NOR_MULTI_DIE flag is set in flash id table use
it to enable split reads to avoid above issue. Define SPI_NOR_MULTI_DIE
new flag to flash id flags. Remove SPI_FLASH_SPLIT_READ config and
related code from the zynq and zynqmp qspi drivers as it is redundant.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
CPM root port driver doesn't use pci_irqd_intx_xlate method
to translate INTx numbers, it expects the device tree node to
provide required mapping.
Modifying interrupt-map property to provide driver with
required hwirq range to be mapped for INTx interrupts.
net: xilinx: axi_mrmac: Backport from upstream code
In this patch backport MRMAC driver from upstream code with comments
addressed from mainline.
Below things are addressed in this patch.
- Changed all static allocations to dynamic and freed them.
- Used setbits_le32 and clrbits_le32 wherever applicable
- All return's are changed to proper error codes instead of 1 or -1
- Changed return type of isrxready() from int to bool
- Changed all printf's to log_warning, and debug to log_debug
- Added function headers with desciption
- Changed all capital hex numbers to small hex numbers
There are couple issues in set_ios function which are introduced when
xlnx code is rebased to mainline U-Boot version 2021.1 with
'commit 880b655d660e ("mmc: zynq_sdhci: Fix UHS 1.8v switching with 5ms
delay")'
Mainline 'commit f12341a95295 ("mmc: sdhci: Fix HISPD bit handling")' is
pulled partially when rebased to 2021.1. Fix it by adding back missing
HISPD bit setting code.
Remove extra line which writes back to sdhc host control register.
set_control_reg call got duplicated after rebase, remove it.
Since, voltage setting function (set_control_reg) is moved to the
beginning of the function, no need to return if the set_ios is called
with clock disable, so remove return.
mmc: zynq_sdhci: Change variable deviceid to node_id
Change deviceid to node_id in arasan_zynqmp_dll_reset() and also in
tapdelay related static inline functions to reflect proper name and
for consistency.
mmc: zynq_sdhci: Move setting tapdelay code to driver
tap_delays.c just has calls to xilinx_pm_request() for setting tapdelays.
Simply move these calls to zynq_sdhci.c and make them static inline.
Similarly zynqmp_tap_delay.h also has call to xilinx_pm_request() for
dll reset. Do the same for this file as well.
arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB node
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.
Add kernel_comp_addr_r, kernel_comp_size env variables for zynqmp and
versal to be able to use the compressed kernel Image(.gz,.bz2,.lzma,.lzo)
using booti command.
mmc: zynq_sdhci: Use pm_node id instead of device sequence id
When programming tapdelays & resetting dll, we are using device
sequence id, which is not programming tapelays & dll reset.
So use pm_node id instead of device sequence id to fix above issue.
Also use u8 instead of u32 for node_id variable as we have pm_node
ids less than 128.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Michal Simek [Mon, 12 Jul 2021 08:56:33 +0000 (10:56 +0200)]
arm64: zynqmp: Remove gpio from aliases list
It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.
The same changes was done by commit d458db3ce900 ("arm64: zynqmp: Remove
gpio from aliases list").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Use new compatible strings for DP snd pcm
To remove a stack trace when removing and reprobing the DP snd pcm,
use the new DP pcm compatible strings to allow the driver to create
standardized names for each DP snd pcm.
xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatiblity string to probe &
initilize flash. With missing compatibility string we are observing
below error:
Zynq> sf probe 0 0 0
jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2)
mtd: spi-nor: Fix read SFDP data in dual parallel mode
Reading the SFDP data is broken in two ways in dual parallel mode in the
current implementation.
1) It reads the data interleaved from both chips, which results in data
that can not be parsed. Since both chips have to be identical for dual
parallel mode the SFDP data will also be identical. So only read the data
from one of the chips.
2) The page, erase and chip size are not update to reflect that they should
be twice as large in dual parallel mode. Fix this by moving the update of
those parameter after running the SFDP detection rather than doing it
before.
In the current implementation dual parallel mode only works for limited
corner cases, but is mostly broken.
For example
* Erase will only erase one of the chips leaving every second byte
non-erased
* Lock/unlock only works if a read is done before it, otherwise it will
timeout
* Using bank/extended address mode (CONFIG_SPI_FLASH_BAR) fails in
`sf probe` with a timeout
This is primarily due to incorrect setting of the striped access. Some
commands that should set it don't set it, while others that do set it
shouldn't set it.
To fix this make sure that the SPI_XFER_STRIPE flag gets set in
spi_nor_init() when operating in dual parallel mode. This means the flag is
always set before issuing any commands that need it.
And then in addition use a list of opcodes for which to disable striped
access (e.g. erase).
This is similar to what the Linux driver does to support dual parallel
mode.
Kunihiko Hayashi [Tue, 15 Jun 2021 06:33:02 +0000 (15:33 +0900)]
arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y
If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled,
wherever original env is placed anywhere, it should be relocated to
the right address.
Relocation offset gd->reloc_off is calculated with SYS_TEXT_BASE in
setup_reloc() and env address gd->env_addr is relocated by the offset in
initr_reloc_global_data().
However, SYS_TEXT_BASE isn't always runtime base address when
POSITION_INDEPENDENT is enabled. So the relocated env_addr might point to
wrong address. For example, if SYS_TEXT_BASE is zero, gd->env_addr is
out of memory location and memory exception will occur.
There is a difference between linked address such as SYS_TEXT_BASE and
runtime base address. In _main, the difference is calculated as
"run-vs-link" offset. The env_addr should also be added to the offset
to fix the address.
Add support for xilinx multirate(MRMAC) ethernet driver.
This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
Added support for 4 ports of MRMAC for speeds 10G and 25G.
MCDMA supports upto 16 channels but in this driver we have setup only
one channel which is enough.
net: ethtool: Add ethernet speed macros for higher speeds
Add speed macro's for higher ethernet speeds to be used in u-boot
networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G,
56G, 100G and 200G inline with linux.
There are lot of accesses to priv data in ofdata_to_platdata, which is
incorrect. Create a platform data structure and use it in
ofdata_to_platdata, then copy all platform data to priv data in probe.
Michal Simek [Mon, 14 Jun 2021 13:12:27 +0000 (15:12 +0200)]
arm64: zynqmp: Remove unused snps,enable-hibernation flag
This property is used only in gadget mode and there were some upstreaming
commnents about disabling it. Also this property is commented in usb0 but
not in usb1. That's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 3 Jun 2021 08:47:04 +0000 (10:47 +0200)]
arm64: zynqmp: Remove gpio from aliases list
It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynqmp_gqspi: Fix issue of reading more than 32bits length
As the flash sizes are increasing day by day, QSPI in dual-parallel mode
can have devices of size > 512MB. In qspi driver we are trying to read
all the data at once using DMA.
The DMA descriptor destination size is only 29bits long.
QSPIDMA_DST_SIZE 0xFF0F0804
BITS: 1:0 Reserved to keep word alignment
BITS: 28:2 Number of 4-byte words the DMA will transfer
BITS: 31:29 Reserved: Returns 0 when read, writes ignored
So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes.
Anything above will overflow this register and will ignore higher bits
above 29 bits.
Change the DMA functionality if the requested size is greater than or
equal to 512MB to read 256MB chunks.
Srinivas Neeli [Mon, 8 Mar 2021 08:35:19 +0000 (14:05 +0530)]
arm64: dts: zynqmp: rtc: Update rtc calibration value
As per the design specification
"The 16-bit Seconds Calibration Value represents the number of
Oscillator Ticks that are required to measure the largest time
period that is less than or equal to 1 second.
For an oscillator that is 32.768 KHz, this value will be 0x7FFF."
Michal Simek [Tue, 26 Jan 2021 14:59:59 +0000 (15:59 +0100)]
arm64: versal: zynqmp: Add support for VPXA2785
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 19 Jan 2021 14:00:45 +0000 (15:00 +0100)]
arm64: versal: zynqmp: Add support for vpk120
Add support for Versal premium evaluation board vpk120.
Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 26 Nov 2020 13:25:03 +0000 (14:25 +0100)]
ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to
json-schema") converted binding to yaml and some missing required
properties started to be reported. Align binding based on it.
The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml
Michal Simek [Thu, 26 Nov 2020 13:25:04 +0000 (14:25 +0100)]
ARM: zynq: Convert at25 binding to new description on zc770-xm013
The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding
document to yaml") converted binding to yaml and 3 deprecated properties
pop up.
The patch is fixing these warnings:
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
>From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml
T Karthik Reddy [Tue, 18 May 2021 14:28:02 +0000 (08:28 -0600)]
mmc: zynq_sdhci: wait till sd card detect state is stable
As per SD spec when SD host controller is reset, it takes 1000msec
to detect the card state. In case, if we enable the sd bus voltage &
card detect state is not stable, then host controller will disable
the sd bus voltage.
In case of warm/subsystem reboot, due to unstable card detect state
host controller is disabling the sd bus voltage to sd card causing
sd card timeout error. So we wait for a maximum of 1000msec to get
the card detect state stable before we enable the sd bus voltage.
This current fix is workaround for now, this needs to be analysed
further. Zynqmp platform should behave the same as Versal, but we
did not encounter this issue as of now. So we are fixing it for
Versal only.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Michal Simek [Thu, 13 May 2021 11:58:58 +0000 (13:58 +0200)]
arm64: zynqmp: Enable EFI secure boot
Enabling EFI secure boot which is required for EBBR specification.
Enabling this will fix
"RT.SetVariable - Create one Time Base Auth Variable, the expect return
status should be EFI_SUCCESS"
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The EFI_LOAD_FILE_PROTOCOL_GUID and EFI_LOAD_FILE2_PROTOCOL_GUID are needed
to complement the implementation of the LoadFile() boot service.
Remove a duplicate declaration of a variable for the
EFI_LOAD_FILE2_PROTOCOL_GUID.
Move the remaining declaration to efi_boottime.c.
Add a variable for the EFI_LOAD_FILE_PROTOCOL_GUID.
efi_loader: resequence functions in efi_boottime.c
For implementing support for the EFI_LOAD_FILE_PROTOCOL in the LoadImage()
service we will have to call the LocateDevicePath() service. To avoid a
forward declaration resequence the functions.
U-Boot expects to be linked to a specific hard-coded address and to
be loaded to and run from that address. CONFIG_POSITION_INDEPENDENT
config lifts that restriction & allowing the code to be loaded to
and executed from almost any address.
As we enabled CONFIG_POSITION_INDEPENDENT, CONFIG_INIT_SP_RELATIVE
is enabled by default, where it will set the early stack pointer at
runtime by adding an offset value to &_bss_start. The offset value
is taken from SYS_INIT_SP_BSS_OFFSET.
SYS_INIT_SP_BSS_OFFSET offset should be large enough so that the
early malloc region, global data (gd), and early stack should fit.
With commit d8fabcc424bd ("arm64: versal: Increase SYS_MALLOC_F_LEN")
SYS_MALLOC_F_LEN is increased from 32KB to 1MB, so we need to
accommodate this space with SYS_INIT_SP_BSS_OFFSET. Hence increasing
SYS_INIT_SP_BSS_OFFSET to 1.5MB.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
projects / thirdparty / u-boot.git / log
