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8 months agolibcpp: modules and -include again
Jason Merrill [Tue, 26 Nov 2024 21:19:05 +0000 (16:19 -0500)] 
libcpp: modules and -include again

I enabled include translation to header units in r15-1104-ga29f481bbcaf2b,
but it seems that patch wasn't sufficient, as any diagnostics in the main
source file would show up as coming from the header instead.

Fixed by setting buffer->file for leaving the file transition that my
previous patch made us enter.  And don't push a buffer of newlines, in this
case that messes up line numbers instead of aligning them.

libcpp/ChangeLog:

* files.cc (_cpp_stack_file): Handle -include of header unit more
specially.

gcc/testsuite/ChangeLog:

* g++.dg/modules/dashinclude-1_b.C: Add an #error.
* g++.dg/modules/dashinclude-1_a.H: Remove dg-module-do run.

8 months agoPR117350: Keep assembler name for abstract decls for autofdo
Andi Kleen [Thu, 31 Oct 2024 17:26:16 +0000 (10:26 -0700)] 
PR117350: Keep assembler name for abstract decls for autofdo

autofdo looks up inline stacks and tries to match them with the profile
data using their symbol name. Make sure all decls that can be in a inline stack
have a valid assembler name.

This fixes a bootstrap problem with autoprofiledbootstrap and LTO.

2024-10-30  Jason Merrill  <jason@redhat.com>
    Andrew Pinski  <quic_apinski@quicinc.com>
    Andi Kleen  <ak@gcc.gnu.org>
gcc/ChangeLog:

PR bootstrap/117350
* tree.cc (need_assembler_name_p): Keep assembler name
for abstract declarations when autofdo is used.

8 months agoDaily bump.
GCC Administrator [Wed, 27 Nov 2024 00:20:18 +0000 (00:20 +0000)] 
Daily bump.

8 months agolibstdc++: Add -fno-assume-sane-operators-new-delete to test [PR117751]
Jonathan Wakely [Mon, 25 Nov 2024 22:40:43 +0000 (22:40 +0000)] 
libstdc++: Add -fno-assume-sane-operators-new-delete to test [PR117751]

libstdc++-v3/ChangeLog:

PR libstdc++/117751
* testsuite/18_support/50594.cc: Edit dg-options to include the
-fno-assume-sane-operators-new-delete option.

8 months agoFortran: fix minor front-end memleaks
Harald Anlauf [Tue, 26 Nov 2024 19:37:35 +0000 (20:37 +0100)] 
Fortran: fix minor front-end memleaks

gcc/fortran/ChangeLog:

* expr.cc (find_inquiry_ref): Fix memleak introduced by scanning
the reference chain to find and simplify inquiry references.
* symbol.cc (gfc_copy_formal_args_intr): Free formal namespace
when not needed to avoid a front-end memleak.

8 months agoaarch64: Update error message check for __builtin_launder check of sve-sizeless-2.C
Andrew Pinski [Tue, 26 Nov 2024 21:38:15 +0000 (13:38 -0800)] 
aarch64: Update error message check for __builtin_launder check of sve-sizeless-2.C

r15-3614-g9fe57e4879de93 changed the error message for __builtin_launder but this testcase
was not updated for the new format of the error message since it is an aarch64 specific
testcase.

This patch updates the expected error message.

Pushed as obvious after testing to see the testcase now works.

gcc/testsuite/ChangeLog:

* g++.dg/ext/sve-sizeless-2.C: Update the expected error message
for __builtin_launder.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agoaarch64: Fix fp8_scalar_1.c's stacktest1
Andrew Pinski [Tue, 26 Nov 2024 21:05:00 +0000 (13:05 -0800)] 
aarch64: Fix fp8_scalar_1.c's stacktest1

The function body test was expecting:
umov w0, v0.b[0]
strb w0, [sp, 15]

But the code generation was improved after r15-5375-gbeec291225be to just:
str b0, [sp, 15]

which is correct and better because no longer need to move between SIMD registers
and the GPRs.
This changes the function body test to new better code generation.

Pushed as obvious after a test of the testcase to make sure it now passes.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/fp8_scalar_1.c (stacktest1): Fix for new
improved code generation.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agoselftest: invoke "diff" when ASSERT_STREQ fails
David Malcolm [Tue, 26 Nov 2024 21:09:37 +0000 (16:09 -0500)] 
selftest: invoke "diff" when ASSERT_STREQ fails

Currently when ASSERT_STREQ or ASSERT_STREQ_AT fail we print
both strings to stderr.  However it can be hard to figure out
the problem (e.g. for 1-character differences in long strings).

Extend the output by writing out the strings to tempfiles and
invoking "diff -up" on them when we have such a selftest failure,
to (I hope) simplify debugging.

gcc/ChangeLog:
* selftest.cc (selftest::print_diff): New function.
(selftest::assert_streq): Call it when we have non-equal
non-null strings.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
8 months agotestsuite: rename plugins from .c to .cc
David Malcolm [Tue, 26 Nov 2024 21:01:35 +0000 (16:01 -0500)] 
testsuite: rename plugins from .c to .cc

In r12-6650-g5c69acb32329d4 we updated our sources from .c to .cc
since for some time GCC has been implemented in C++, not C.

GCC plugins are also implemented in C++, not C, but the plugins
in our testsuite still have .c extensions.

Rename the plugin implementation files in the testsuite from .c to .cc,
for consistency with GCC's implementation files (as opposed to .C,
which is used in C++ parts of the testsuite).

Don't rename the files that the plugins are tested *on*.

gcc/testsuite/ChangeLog:
* g++.dg/plugin/plugin.exp (plugin_test_list): Update for renaming
of all plugin implementation files from .c to .cc.
* g++.dg/plugin/attribute_plugin.c: Rename to...
* g++.dg/plugin/attribute_plugin.cc: ...this.
* g++.dg/plugin/comment_plugin.c: Rename to...
* g++.dg/plugin/comment_plugin.cc: ...this.
* g++.dg/plugin/decl_plugin.c: Rename to...
* g++.dg/plugin/decl_plugin.cc: ...this.
* g++.dg/plugin/def_plugin.c: Rename to...
* g++.dg/plugin/def_plugin.cc: ...this.
* g++.dg/plugin/dumb_plugin.c: Rename to...
* g++.dg/plugin/dumb_plugin.cc: ...this.
* g++.dg/plugin/header_plugin.c: Rename to...
* g++.dg/plugin/header_plugin.cc: ...this.
* g++.dg/plugin/pragma_plugin.c: Rename to...
* g++.dg/plugin/pragma_plugin.cc: ...this.
* g++.dg/plugin/selfassign.c: Rename to...
* g++.dg/plugin/selfassign.cc: ...this.
* g++.dg/plugin/show_template_tree_color_plugin.c: Rename to...
* g++.dg/plugin/show_template_tree_color_plugin.cc: ...this.
* gcc.dg/plugin/plugin.exp (plugin_test_list): Update for renaming
of all plugin implementation files from .c to .cc.
* gcc.dg/plugin/analyzer_cpython_plugin.c: Rename to...
* gcc.dg/plugin/analyzer_cpython_plugin.cc: ...this.
* gcc.dg/plugin/analyzer_gil_plugin.c: Rename to...
* gcc.dg/plugin/analyzer_gil_plugin.cc: ...this.
* gcc.dg/plugin/analyzer_kernel_plugin.c: Rename to...
* gcc.dg/plugin/analyzer_kernel_plugin.cc: ...this.
* gcc.dg/plugin/analyzer_known_fns_plugin.c: Rename to...
* gcc.dg/plugin/analyzer_known_fns_plugin.cc: ...this.
* gcc.dg/plugin/crash_test_plugin.c: Rename to...
* gcc.dg/plugin/crash_test_plugin.cc: ...this.
* gcc.dg/plugin/diagnostic_group_plugin.c: Rename to...
* gcc.dg/plugin/diagnostic_group_plugin.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_show_trees.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_show_trees.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_inlining.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_inlining.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_metadata.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_metadata.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_nesting.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_nesting.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_paths.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_paths.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_show_locus.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_show_locus.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_string_literals.c: Rename
* gcc.dg/plugin/diagnostic_plugin_test_string_literals.cc: ..to
this.
* gcc.dg/plugin/diagnostic_plugin_test_text_art.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_text_art.cc: ...this.
* gcc.dg/plugin/diagnostic_plugin_test_tree_expression_range.c:
Rename to...
* gcc.dg/plugin/diagnostic_plugin_test_tree_expression_range.cc:
...this.
* gcc.dg/plugin/diagnostic_plugin_xhtml_format.c: Rename to...
* gcc.dg/plugin/diagnostic_plugin_xhtml_format.cc: ...this.
* gcc.dg/plugin/dump_plugin.c: Rename to...
* gcc.dg/plugin/dump_plugin.cc: ...this.
* gcc.dg/plugin/expensive_selftests_plugin.c: Rename to...
* gcc.dg/plugin/expensive_selftests_plugin.cc: ...this.
* gcc.dg/plugin/finish_unit_plugin.c: Rename to...
* gcc.dg/plugin/finish_unit_plugin.cc: ...this.
* gcc.dg/plugin/ggcplug.c: Rename to...
* gcc.dg/plugin/ggcplug.cc: ...this.
* gcc.dg/plugin/location_overflow_plugin.c: Rename to...
* gcc.dg/plugin/location_overflow_plugin.cc: ...this.
* gcc.dg/plugin/must_tail_call_plugin.c: Rename to...
* gcc.dg/plugin/must_tail_call_plugin.cc: ...this.
* gcc.dg/plugin/one_time_plugin.c: Rename to...
* gcc.dg/plugin/one_time_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-01_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-01_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-02_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-02_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-03_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-03_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-04_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-04_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-05_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-05_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-06_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-06_plugin.cc: ...this.
* gcc.dg/plugin/poly-int-07_plugin.c: Rename to...
* gcc.dg/plugin/poly-int-07_plugin.cc: ...this.
* gcc.dg/plugin/selfassign.c: Rename to...
* gcc.dg/plugin/selfassign.cc: ...this.
* gcc.dg/plugin/start_unit_plugin.c: Rename to...
* gcc.dg/plugin/start_unit_plugin.cc: ...this.
* gcc.dg/plugin/wide-int_plugin.c: Rename to...
* gcc.dg/plugin/wide-int_plugin.cc: ...this.
* obj-c++.dg/plugin/plugin.exp: Update for renaming of plugin
implementation file from .c to .cc.
* objc.dg/plugin/plugin.exp: Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
8 months agocsky: use quotes when referring to cpus and archs [PR90160]
David Malcolm [Tue, 26 Nov 2024 20:58:25 +0000 (15:58 -0500)] 
csky: use quotes when referring to cpus and archs [PR90160]

gcc/ChangeLog:
PR translation/90160
* config/csky/csky.cc (csky_configure_build_target): Use %qs when
referring to cpu and arch names.
(csky_option_override): Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
8 months ago[PATCH] testsuite:RISC-V:Modify the char string.
yulong [Tue, 26 Nov 2024 17:36:44 +0000 (10:36 -0700)] 
[PATCH] testsuite:RISC-V:Modify the char string.

From: yulong <shiyulong@iscas.ac.cn>

This patch modifies the char string from __riscv_xsfvcp to __riscv_xsfcease.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-sf-2.c: Modify the char string.

8 months agoFortran: passing inquiry ref of complex array to assumed rank dummy [PR117774]
Harald Anlauf [Mon, 25 Nov 2024 21:55:10 +0000 (22:55 +0100)] 
Fortran: passing inquiry ref of complex array to assumed rank dummy [PR117774]

PR fortran/117774

gcc/fortran/ChangeLog:

* trans-expr.cc (gfc_conv_procedure_call): When passing an array
to an assumed-rank dummy, terminate search for array reference of
actual argument before an inquiry reference (e.g. INQUIRY_RE,
INQUIRY_IM) so that bounds update works properly.

gcc/testsuite/ChangeLog:

* gfortran.dg/assumed_rank_25.f90: New test.

8 months agoc: avoid double-negative in warning message [PR94370]
David Malcolm [Tue, 26 Nov 2024 15:39:48 +0000 (10:39 -0500)] 
c: avoid double-negative in warning message [PR94370]

gcc/c/ChangeLog:
PR c/94370
* c-typeck.cc (c_build_functype_attribute_variant): Reword
warning message to avoid double-negative.

gcc/testsuite/ChangeLog:
PR c/94370
* gcc.dg/format/proto.c: Update wording of message.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
8 months agoloop-prefetch: fix wording of warning [PR80760]
David Malcolm [Tue, 26 Nov 2024 15:39:18 +0000 (10:39 -0500)] 
loop-prefetch: fix wording of warning [PR80760]

gcc/ChangeLog:
PR translation/80760
* tree-ssa-loop-prefetch.cc (pass_loop_prefetch::execute): Add
missing colon to not-a-power-of-two param warning.

gcc/testsuite/ChangeLog:
PR translation/80760
* gcc.dg/tree-ssa/pr79803.c: Add ':' to expected warning.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
8 months agoplugin: add missing colon in error message [PR93746]
David Malcolm [Tue, 26 Nov 2024 15:39:12 +0000 (10:39 -0500)] 
plugin: add missing colon in error message [PR93746]

gcc/ChangeLog:
PR plugins/93746
* plugin.cc (try_init_one_plugin): Add missing colon in error
message.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
8 months agogdbhooks: Handle references to vec* in VecPrinter
Alex Coplan [Tue, 26 Nov 2024 15:10:29 +0000 (15:10 +0000)] 
gdbhooks: Handle references to vec* in VecPrinter

vec.h has this method:

  template<typename T, typename A>
  inline T *
  vec_safe_push (vec<T, A, vl_embed> *&v, const T &obj CXX_MEM_STAT_INFO)

where v is a reference to a pointer to vec.  This matches the regex for
VecPrinter, so gdbhooks.py attempts to print it but chokes on the reference.
I see the following:

  #1  0x0000000002b84b7b in vec_safe_push<edge_def*, va_gc> (v=Traceback (most
  recent call last):
    File "$SRC/gcc/gcc/gdbhooks.py", line 486, in to_string
      return '0x%x' % intptr(self.gdbval)
    File "$SRC/gcc/gcc/gdbhooks.py", line 168, in intptr
      return long(gdbval) if sys.version_info.major == 2 else int(gdbval)
  gdb.error: Cannot convert value to long.

This patch makes VecPrinter handle such references by stripping them
(dereferencing) at the top of the relevant functions.

gcc/ChangeLog:

* gdbhooks.py (strip_ref): New. Use it ...
(VecPrinter.to_string): ... here,
(VecPrinter.children): ... and here.

8 months agoRISC-V: Refactor the testcases for RVV gather/scatter
Pan Li [Mon, 25 Nov 2024 03:45:30 +0000 (11:45 +0800)] 
RISC-V: Refactor the testcases for RVV gather/scatter

This patch would like to refactor the testcases of gather/scatter
after sorts of optimization option passing to testcase.  Includes:

* Remove unnecessary optimization options.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
  on different optimization options (like O2, O3).

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c:
Adjust the dump check times.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c:
Remove unnecessary option and add target no-opts/any-tops.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Fix incorrect optimization options passing to gather/scatter
Pan Li [Mon, 25 Nov 2024 03:45:29 +0000 (11:45 +0800)] 
RISC-V: Fix incorrect optimization options passing to gather/scatter

Like the strided load/store, the testcases of vector gather/scatter are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.  This patch
would like to make it correct almost the same as what we fixed for
strided load/store.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
options passing to testcases.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoimprove std::deque::_M_reallocate_map
Jan Hubicka [Tue, 26 Nov 2024 12:52:09 +0000 (13:52 +0100)] 
improve std::deque::_M_reallocate_map

Looking into reason why we still do throw_bad_alloc in clang binary I noticed
that quite few calls come from deque::_M_reallocate_map.  This patch adds
unreachable to limit the size of realloc_map.  _M_reallocate_map is called only
if new size is smaller then max_size.  map is an array holding pointers to
entries of fixed size.

Since rellocation is done by doubling the map size, I think the maximal size of
map allocated is max_size / deque_buf_size rounded up times two.  This should
be also safe for overflows since we have extra bit.

map size is always at least 8. Theoretically this computation may be wrong for
very large T, but in that case callers should never reallocate.

On the testcase I get:
jh@shroud:~> ~/trunk-install-new4/bin/g++ -O2 dq.C -c ; size -A dq.o | grep text
.text                                              284      0
.text._ZNSt5dequeIiSaIiEE17_M_reallocate_mapEmb    485      0
.text.unlikely                                      10      0
jh@shroud:~> ~/trunk-install-new5/bin/g++ -O2 dq.C -c ; size -A dq.o | grep text
.text                                              284      0
.text._ZNSt5dequeIiSaIiEE17_M_reallocate_mapEmb    465      0
.text.unlikely                                      10      0

so this saves about 20 bytes of rellocate_map, which I think is worthwhile.
Curiously enough gcc14 does:

jh@shroud:~> g++ -O2 dq.C -c ; size -A dq.o | grep text
.text                 604      0
.text.unlikely         10      0

which is 145 bytes smaller. Obvoius difference is that _M_reallocate_map gets inlined.
Compiling gcc14 preprocessed file with trunk gives:

jh@shroud:~> g++ -O2 dq.C -S ; size -A dq.o | grep text
.text                 762      0
.text.unlikely         10      0

So inlining is due to changes at libstdc++ side, but code size growth is due to
something else.

For clang this reduced number of thris_bad_new_array_length from 121 to 61.

libstdc++-v3/ChangeLog:

* include/bits/deque.tcc (std::deque::_M_reallocate_map): Add
__builtin_unreachable check to declare that maps are not very large.
* include/bits/stl_deque.h (std::deque::size): Add __builtin_unreachable
to check for maximal size of map.

gcc/testsuite/ChangeLog:

* g++.dg/tree-ssa/deque-1.C: New test.
* g++.dg/tree-ssa/deque-2.C: New test.

8 months agoada: Do not use ATTR_ADDR_EXPR for 'Unrestricted_Access
Eric Botcazou [Mon, 11 Nov 2024 10:16:26 +0000 (11:16 +0100)] 
ada: Do not use ATTR_ADDR_EXPR for 'Unrestricted_Access

Unlike for 'Access or 'Unchecked_Access, the Attribute_to_gnu routine passes
ATTR_ADDR_EXPR to build_unary_op for 'Unrestricted_Access, which causes the
processing done in build_unary_op to flatten the reference, in particular to
remove all intermediate (view) conversions, which may be problematic for the
SUBSTITUTE_PLACEHOLDER_IN_EXPR machinery.

gcc/ada/ChangeLog:

* gcc-interface/trans.cc (Attribute_to_gnu) <Attr_Access>: Do not
pass ATTR_ADDR_EXPR to build_unary_op for 'Unrestricted_Access.

8 months agoada: Add minimal support for address clause/aspect on controlled objects
Eric Botcazou [Tue, 12 Nov 2024 18:46:12 +0000 (19:46 +0100)] 
ada: Add minimal support for address clause/aspect on controlled objects

The clause and aspect have been accepted by the compiler for a few years,
but the result is generally an internal compiler error or an incorrect
finalization at run time.

gcc/ada/ChangeLog:

* exp_ch3.adb (Expand_N_Object_Declaration): Do not insert the tag
assignment there if the object has the Address aspect.
* exp_ch7.adb: Add clauses for Aspect package.
(Build_Finalizer.Process_Object_Declaration): Deal with an object
with delayed freezing.
(Insert_Actions_In_Scope_Around): If the target is the declaration
of an object with address clause or aspect, move all the statements
that have been inserted after it into the Initialization_Statements
list of the object.
* freeze.adb (Check_Address_Clause): Do not reassign the tag here,
instead set the appropriate flag on the assignment statement.

8 months agoada: Clean up previous change
Eric Botcazou [Wed, 13 Nov 2024 15:37:32 +0000 (16:37 +0100)] 
ada: Clean up previous change

gcc/ada/ChangeLog:

* sem_res.adb (Valid_Conversion): Do not initialize Opnd_Type before
calling Get_Corresponding_Mutably_Tagged_Type_If_Present.

8 months agoada: Minor adjustments to error message for RM B.1(24)
Eric Botcazou [Wed, 13 Nov 2024 08:42:01 +0000 (09:42 +0100)] 
ada: Minor adjustments to error message for RM B.1(24)

The RM B.1(24) sub-clause says that imported entities cannot be initialized
and it is checked in three contexts, aspect Import, pragma Import and pragma
Import_Object, with slightly different error messages.  Moreover, for the
aspect, the error is given twice because that of the pragma is also given.

In addition, if the initialization expression is an aggregate that is not
static, the error is given only for the aspect and not for the two pragmas.

This change aligns the error messages on that of pragma Import and plugs the
aforementioned loophole for the two pragmas.

gcc/ada/ChangeLog:

* sem_ch13.adb (Analyze_Aspect_Export_Import): Add explicit mention
of the declaration in the error message for the Import.
* sem_prag.adb (Process_Extended_Import_Export_Object_Pragma): Also
test Has_Init_Expression on the declaration node for Import_Object
and use the same wording as that of Import.
(Process_Import_Or_Interface): Also test Has_Init_Expression on the
declaration node for Import.

8 months agoada: Refactor code of Check_Ambiguous_Call and Valid_Conversion
Javier Miranda [Tue, 29 Oct 2024 08:31:28 +0000 (08:31 +0000)] 
ada: Refactor code of Check_Ambiguous_Call and Valid_Conversion

Code cleanup; factorizing code.

gcc/ada/ChangeLog:

* sem_ch2.adb (Check_Ambiguous_Call): Replace code factorized
code by call to the new subprogram Is_Ambiguous_Operand.
* sem_res.ads (Is_Ambiguous_Operand): New subprogram that
factorizes previous code in Check_Ambiguous_Call and
Valid_Conversion.
* sem_res.adb (Is_Ambiguous_Operand): New subprogram.
(Valid_Tagged_Conversion): Replace factorized code by call to
the new subprogram Is_Ambiguous_Operand.
(Report_Error_N): New subprogram.
(Report_Error_NE): New subprogram.
(Report_Interpretation): New subprogram.
(Conversion_Error_N): Removed; replaced by Report_Error_N.
(Conversion_Error_NE): Removed; replaced by Report_Error_NE.
(Valid_Conversion): Update Opnd_Type after the call to
Is_Ambiguous_Operand in the overloaded case.

8 months agoada: Relocate implementation of Write_Error_Summary
Viljar Indus [Tue, 12 Nov 2024 11:11:00 +0000 (13:11 +0200)] 
ada: Relocate implementation of Write_Error_Summary

Reuse the same implementation in Errout and Errutil.

gcc/ada/ChangeLog:

* errout.adb: Remove implmentation of Write_Error_Summary.
* erroutc.adb: Add implemenetation of Write_Error_Summary.
* erroutc.ads: Add spec of Write_Error_Summary.
* errutil.adb: Remove implementation for writing the error summary.

8 months agoada: Relocate implementation of Set_Msg_Insertion_Column
Viljar Indus [Tue, 12 Nov 2024 10:32:05 +0000 (12:32 +0200)] 
ada: Relocate implementation of Set_Msg_Insertion_Column

The implementation was duplicated in errout and errutil. Move
the implementation to erroutc where other similar commonly used
functions are.

gcc/ada/ChangeLog:

* errout.adb: Remove implemntation of Set_Msg_Insertion_Column.
* erroutc.adb: Add implementation of Set_Msg_Insertion_Column.
* erroutc.ads: Add spec of Set_Msg_Insertion_Column.
* errutil.adb: Remove implementation of Set_Msg_Insertion_Column.

8 months agoada: Remove Warn_Runtime_Raise attribute from Error_Msg_Object
Viljar Indus [Mon, 11 Nov 2024 09:01:12 +0000 (11:01 +0200)] 
ada: Remove Warn_Runtime_Raise attribute from Error_Msg_Object

The goal of this attribute is to raise a warning to an error when
the -gnatwE flag is used. This is similar to the existing warnings
as error behavior under the Warn_Err flag so it can be merged.

gcc/ada/ChangeLog:

* errout.adb: Set Warn_Err as true if Is_Runtime_Error was
set in the error message.
* erroutc.adb: Remove instances of Warn_Runtime_Raise.
* erroutc.ads: Likewise.
* errutil.adb: Likewise.

8 months agoada: Refactor checking redundant messages
Viljar Indus [Mon, 11 Nov 2024 08:19:21 +0000 (10:19 +0200)] 
ada: Refactor checking redundant messages

Move common code between errout and errutil into a single function.

gcc/ada/ChangeLog:

* errout.adb: Use Is_Redundant_Error_Message.
* erroutc.adb: Move the common code for checking if a message
can be removed to Is_Redundant_Error_Message.
* erroutc.ads: Add definition of Is_Redundant_Error_Message.
* errutil.adb: Use Is_Redundant_Error_Message.

8 months agoada: Remove Current_Node from Errout
Viljar Indus [Tue, 5 Nov 2024 08:42:55 +0000 (10:42 +0200)] 
ada: Remove Current_Node from Errout

This variable was used for Opt.Include_Subprogram_In_Messages
activated by -gnatdJ. This switch has been removed so this variable
is no longer used.

gcc/ada/ChangeLog:

* errout.ads: Remove Current_Node.
* errout.adb: Remove uses of Current_Node.
* par-ch6.adb: Same as above.
* par-ch7.adb: Same as above.
* par-ch9.adb: Same as above.

8 months agoada: Remove Raise_Exception_On_Error
Viljar Indus [Mon, 4 Nov 2024 12:16:02 +0000 (14:16 +0200)] 
ada: Remove Raise_Exception_On_Error

Raise_Exception_On_Error is never modified so it can be removed.

gcc/ada/ChangeLog:

* err_vars.ads: Remove Raise_Exception_On_Error and
Error_Msg_Exception.
* errout.ads: Same as above.
* errout.adb: Remove uses of Raise_Exception_On_Error and
Error_Msg_Exception.
* errutil.adb: Same as above.

8 months agoada: Store error message kind as an enum
Viljar Indus [Thu, 31 Oct 2024 13:50:46 +0000 (15:50 +0200)] 
ada: Store error message kind as an enum

Simplify the storage for the kind of error message under a single
enumerator. This replaces the existing attributes with the following
enumeration values.
* Is_Warning_Msg => Warning
* Is_Style_Msg => Style
* Is_Info_Msg => Info
* Is_Check_Msg => Low_Check, Medium_Check, High_Check
* Is_Serious_Error => Error, if the attribute was false then
  Non_Serious_Error.

gcc/ada/ChangeLog:

* diagnostics-converter.adb: Use new enum values instead
of the old attributes.
* diagnostics-switch_repository.adb: Same as above.
* diagnostics-utils.adb: Same as above.
* diagnostics.adb: Same as above.
* diagnostics.ads: Same as above.
* errout.adb: Same as above.
* erroutc.adb: Same as above.
* erroutc.ads: Remove old attriubtes and replace them
with Error_Msg_Kind.
* errutil.adb: Same as others.

8 months agoada: Refactor code for printing the error location
Viljar Indus [Fri, 1 Nov 2024 11:15:21 +0000 (13:15 +0200)] 
ada: Refactor code for printing the error location

gcc/ada/ChangeLog:

* errout.adb: Use Output_Msg_Location
* erroutc.adb: add common implementation for printing the
error message line.
* erroutc.ads: Add new method Output_Msg_Location
* errutil.adb: use Output_Msg_Location

8 months agoada: Simplify code
Viljar Indus [Mon, 16 Sep 2024 09:14:00 +0000 (12:14 +0300)] 
ada: Simplify code

gcc/ada/ChangeLog:

* diagnostics-converter.adb: Remove uses of Info_Warning type. Use
common constructors to simplify implementation.
* diagnostics-pretty_emitter.adb: Remove Info_Warning type.
* diagnostics-utils.adb: Remove uses of Info_Warning.
* diagnostics.adb: Simplify implementation of Primary_Location.
* diagnostics.ads: Remove Info_Warning type.

8 months agoada: Fix the file documenting the ali format
Jose Ruiz [Tue, 12 Nov 2024 11:22:55 +0000 (12:22 +0100)] 
ada: Fix the file documenting the ali format

gcc/ada/ChangeLog:

* doc/gnat_ugn/the_gnat_compilation_model.rst: The format of
the ali file is documented in lib-writ.ads.
* gnat_ugn.texi: Regenerate.

8 months agoada: Change specifications of Uname subprograms
Ronan Desplanques [Tue, 12 Nov 2024 15:09:13 +0000 (16:09 +0100)] 
ada: Change specifications of Uname subprograms

The old specifications were ambiguous as to whether they expected
actuals to have %s/%b suffixes. The new specifications also increases
modularity across the board.

gcc/ada/ChangeLog:

* uname.ads (Is_Internal_Unit_Name, Is_Predefined_Unit_Name): Change
specifications to take a Unit_Name_Type as input.
(Encoded_Library_Unit_Name): New subprogram.
(Is_Predefined_Unit_Name): New overloaded subprogram.
(Get_External_Unit_Name_String): Make use of new
Encoded_Library_Unit_Name subprogram.
* uname.adb (Is_Internal_Unit_Name, Is_Predefined_Unit_Name): Adapt
bodies to specification changes.
* fname-uf.adb (Get_File_Name): Adapt to Uname interface changes.

8 months agoada: Remove use of global name buffer
Ronan Desplanques [Tue, 12 Nov 2024 12:35:17 +0000 (13:35 +0100)] 
ada: Remove use of global name buffer

Before this patch, the body of Fname.UF.Get_File_Name did a lot of
juggling with the global name buffer, which made it hard to understand.
This patch makes the body use local buffers instead.

gcc/ada/ChangeLog:

* fname-uf.adb (Get_File_Name): Use local name buffers.

8 months agoada: Clean up utility function
Ronan Desplanques [Tue, 12 Nov 2024 08:31:35 +0000 (09:31 +0100)] 
ada: Clean up utility function

This patch makes Sem_Util.Get_Library_Unit_Name use Uname more idiomatically.

gcc/ada/ChangeLog:

* sem_util.adb (Get_Library_Unit_Name): Improve use of Uname.

8 months agoada: Fix latent issue exposed by recent change in aggregate expansion
Eric Botcazou [Mon, 11 Nov 2024 23:18:00 +0000 (00:18 +0100)] 
ada: Fix latent issue exposed by recent change in aggregate expansion

The tag is not assigned when a compile-time known aggregate initializes an
object declared with an address clause/aspect.

gcc/ada/ChangeLog:

* freeze.adb: Remove clauses for Exp_Ch3.
(Check_Address_Clause): Always reassign the tag for an object of a
tagged type if there is an initialization expression.

8 months agoFortran: Partial reversion of r15-5083 [PR117763]
Paul Thomas [Tue, 26 Nov 2024 08:58:21 +0000 (08:58 +0000)] 
Fortran: Partial reversion of r15-5083 [PR117763]

2024-11-26  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/117763
* trans-array.cc (gfc_get_array_span): Guard against derefences
of 'expr'. Clean up some typos. Use 'gfc_get_vptr_from_expr'
for clarity and apply a functional reversion of last section
that deals with class dummies.

gcc/testsuite/
PR fortran/117763
* gfortran.dg/pr117763.f90: New test.

8 months agoRISC-V: avlprop: Do not propagate VL from slidedown.
Robin Dapp [Mon, 25 Nov 2024 11:40:53 +0000 (12:40 +0100)] 
RISC-V: avlprop: Do not propagate VL from slidedown.

In the following situation (found in the
rvv/autovec/vls-vlmax/shuffle-slide.c test which is not yet pushed)

vsetivli zero,4,e8,mf4,ta,ma
vle8.v v2,0(a1) # (1)
vle8.v v1,0(a2) # (2)
vsetivli zero,2,e8,mf4,tu,ma
vslidedown.vi v1,v2,2
vsetivli zero,4,e8,mf4,ta,ma
vse8.v v1,0(a2)

we wrongly "propagate" VL=2 from vslidedown into the load.

Although we check whether the "target" instruction has a merge operand
the check only handles cases where the merge operand itself is
loaded, like (2) in the snippet above.  For (1) we load the non-merged
operand, assume propagation is valid and continue despite (2).

This patch just re-uses avl_can_be_propagated_p in order to disable
slides altogether in such situations.

gcc/ChangeLog:

* config/riscv/riscv-avlprop.cc (pass_avlprop::get_vlmax_ta_preferred_avl):
Check whether the use insn is valid for propagation.

8 months agobuiltins: Fix up DFP ICEs on __builtin_fpclassify [PR102674]
Jakub Jelinek [Tue, 26 Nov 2024 08:46:51 +0000 (09:46 +0100)] 
builtins: Fix up DFP ICEs on __builtin_fpclassify [PR102674]

This patch is similar to the one I've just posted, __builtin_fpclassify also
needs to print decimal float minimum differently and use real_from_string3.
Plus I've done some formatting fixes.

2024-11-26  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/102674
* builtins.cc (fold_builtin_fpclassify): Use real_from_string3 rather
than real_from_string.  Use "1E%d" format string rather than "0x1p%d"
for decimal float minimum.  Formatting fixes.

* gcc.dg/dfp/pr102674.c: New test.

8 months agobuiltins: Fix up DFP ICEs on __builtin_is{inf,finite,normal} [PR43374]
Jakub Jelinek [Tue, 26 Nov 2024 08:45:21 +0000 (09:45 +0100)] 
builtins: Fix up DFP ICEs on __builtin_is{inf,finite,normal} [PR43374]

__builtin_is{inf,finite,normal} builtins ICE on _Decimal{32,64,128,64x}
operands unless those operands are constant.

The problem is that we fold the builtins to comparisons with the largest
finite number, but
a) get_max_float was only handling binary floats
b) real_from_string again assumes binary float
and so we were ICEing in the build_real called after the two calls.

This patch adds decimal handling into get_max_float (well, moves it
from c-cppbuiltin.cc which was printing those for __DEC{32,64,128}_MAX__
macros) and uses real_from_string3 (perhaps it is time to rename it
to just real_from_string now that we can use function overloading)
so that it handles both binary and decimal floats.

2024-11-26  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/43374
gcc/
* real.cc (get_max_float): Handle decimal float.
* builtins.cc (fold_builtin_interclass_mathfn): Use
real_from_string3 rather than real_from_string.  Use
"1E%d" format string rather than "0x1p%d" for decimal
float minimum.
gcc/c-family/
* c-cppbuiltin.cc (builtin_define_decimal_float_constants): Use
get_max_float.
gcc/testsuite/
* gcc.dg/dfp/pr43374.c: New test.

8 months agoaffine: Remove unused variable rem from wide_int_constant_multiple_p
Andrew Pinski [Tue, 26 Nov 2024 08:37:33 +0000 (00:37 -0800)] 
affine: Remove unused variable rem from wide_int_constant_multiple_p

This might fix the current bootstrap failure on aarch64, I only tested it
on x86_64. But the rem variable is unused and the for poly_widest_int, there
could be loop if NUM_POLY_INT_COEFFS is 2 or more. In the case of aarch64,
NUM_POLY_INT_COEFFS is 2.
Note the reason why there is warning for the unused variable is due to the deconstructor.

Pushed as obvious after a build for x86_64-linux-gnu.

gcc/ChangeLog:

* tree-affine.cc (wide_int_constant_multiple_p): Remove unused rem variable.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agolibstdc++: Add conditional noexcept to range access functions
Jonathan Wakely [Mon, 25 Nov 2024 21:22:12 +0000 (21:22 +0000)] 
libstdc++: Add conditional noexcept to range access functions

As an extension, this adds conditional noexcept to std::begin, std::end,
and std::ssize.

libstdc++-v3/ChangeLog:

* include/bits/range_access.h (begin, end, ssize): Add
conditional noexcept.
* testsuite/18_support/initializer_list/range_access.cc: Check
results and noexcept-specifier for std::begin and std::end.
* testsuite/24_iterators/headers/iterator/range_access_c++11.cc:
Check for conditional noexcept on std::begin and std::end.
* testsuite/24_iterators/headers/iterator/range_access_c++14.cc:
Likewise.
* testsuite/24_iterators/headers/iterator/range_access_c++17.cc:
Likewise.
* testsuite/24_iterators/range_access/range_access.cc: Check
conditional noexcept is correct.
* testsuite/24_iterators/range_access/range_access_cpp17.cc:
Check std::size, std::empty and std::data.
* testsuite/24_iterators/range_access/range_access_cpp20.cc:
Check conditional noexcept on std::ssize.

8 months agolibstdc++: Improve Doxygen comments in <forward_list>
Jonathan Wakely [Mon, 25 Nov 2024 16:21:01 +0000 (16:21 +0000)] 
libstdc++: Improve Doxygen comments in <forward_list>

Use Markdown backticks to format comments, instead of Doxygen @c and @a
commands.

libstdc++-v3/ChangeLog:

* include/bits/forward_list.h: Use Markdown in Doxygen comments.

8 months agolibstdc++: Move std::error_category symbol to separate file [PR117630]
Jonathan Wakely [Sun, 17 Nov 2024 20:46:07 +0000 (20:46 +0000)] 
libstdc++: Move std::error_category symbol to separate file [PR117630]

As described in PR 117630 the cow-stdexcept.cc file pulls in symbols
from system_error.cc, which are not actually needed there. Moving the
definition of error_category::_M_message to a separate file should solve
it.

libstdc++-v3/ChangeLog:

PR libstdc++/117630
* src/c++11/Makefile.am: Add new file.
* src/c++11/Makefile.in: Regnerate.
* src/c++11/cow-stdexcept.cc (error_category::_M_message): Move
member function definition to ...
* src/c++11/cow-system_error.cc: New file.

8 months agoOptimize 128-bit vector permutation with pand, pandn and por.
Cui, Lili [Tue, 26 Nov 2024 07:10:23 +0000 (15:10 +0800)] 
Optimize 128-bit vector permutation with pand, pandn and por.

This patch introduces a new subroutine in ix86_expand_vec_perm_const_1.
On x86, use mixed constant permutation for V8HImode and V16QImode when
SSE2 is supported. This patch handles certain vector shuffle operations
more efficiently using pand, pandn, and por. This change is intended to
improve assembly code generation for configurations that support SSE2.

gcc/ChangeLog:

PR target/116675
* config/i386/i386-expand.cc (expand_vec_perm_pand_pandn_por):
New subroutine.
(ix86_expand_vec_perm_const_1): Call expand_vec_perm_pand_pandn_por.

gcc/testsuite/ChangeLog:

PR target/116675
* gcc.target/i386/pr116675.c: New test.

8 months agoi386/testsuite: Correct AVX10.2 FP8 test mask usage
Haochen Jiang [Fri, 22 Nov 2024 07:57:47 +0000 (15:57 +0800)] 
i386/testsuite: Correct AVX10.2 FP8 test mask usage

Under FP8, we should not use AVX512F_LEN_HALF to get the mask size since
it will get 16 instead of 8 and drop into wrong if condition. Correct
the usage for vcvtneph2[b,h]f8[,s] runtime test.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_2-512-vcvtneph2bf8-2.c: Correct 128bit
mask usage.
* gcc.target/i386/avx10_2-512-vcvtneph2bf8s-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2hf8-2.c: Ditto.
* gcc.target/i386/avx10_2-512-vcvtneph2hf8s-2.c: Ditto.

8 months agoc: Fix ICEs from invalid atomic compound assignment [PR98195, PR117755]
Joseph Myers [Tue, 26 Nov 2024 03:25:44 +0000 (03:25 +0000)] 
c: Fix ICEs from invalid atomic compound assignment [PR98195, PR117755]

As reported in bug 98195, there are ICEs from an _Atomic compound
assignment with an incomplete type on the RHS, arising from an invalid
temporary being created with such a type.  As reported in bug 117755,
there are also (different) ICEs in cases with complete types where the
binary operation itself is invalid, when inside a nested function,
arising from a temporary being created for the RHS, but then not used
because the binary operation returns error_mark_node, resulting in the
temporary not appearing in a TARGET_EXPR, never getting its
DECL_CONTEXT set by the gimplifier and eventually resulting in an ICE
in nested function processing (trying to find a function context for
the temporary) as a result.

Fix the first ICE with an earlier check for a complete type for the
RHS of an assignment so the problematic temporary is never created for
an incomplete type (which changes the error message three existing
tests get for that case; the new message seems as good as the old
one).  Fix the second ICE by ensuring that once a temporary has been
created, it always gets a corresponding TARGET_EXPR even on error.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

PR c/98195
PR c/117755

gcc/c/
* c-typeck.cc (build_atomic_assign): Always create a TARGET_EXPR
for newval even in case of error from binary operation.
(build_modify_expr): Check early for incomplete type of rhs.

gcc/testsuite/
* gcc.dg/pr98195-1.c, gcc.dg/pr117755-1.c: New tests.
* gcc.dg/noncompile/20020207-1.c, gcc.dg/pr14765-1.c,
objc.dg/method-11.m: Update expected error messages.

8 months agoDaily bump.
GCC Administrator [Tue, 26 Nov 2024 00:19:26 +0000 (00:19 +0000)] 
Daily bump.

8 months agoPR modula2/117777: m2 does not allow single const string in asm volatile
Gaius Mulley [Mon, 25 Nov 2024 22:46:16 +0000 (22:46 +0000)] 
PR modula2/117777: m2 does not allow single const string in asm volatile

gm2 does not allow single const string in ASM VOLATILE.  The bugfix is to
modify AsmOperands in all passes except P3Build.bnf (which is correct).
The remaining passes need to make the term following the ConstExpression
optional.

gcc/m2/ChangeLog:

PR modula2/117777
* gm2-compiler/P0SyntaxCheck.bnf (AsmOperands): Allow term after
ConstExpression to be optional.
* gm2-compiler/P1Build.bnf (AsmOperands): Ditto.
* gm2-compiler/P2Build.bnf (AsmOperands): Ditto.
* gm2-compiler/PCBuild.bnf (AsmOperands): Ditto.
* gm2-compiler/PHBuild.bnf (AsmOperands): Ditto.

gcc/testsuite/ChangeLog:

PR modula2/117777
* gm2/extensions/asm/pass/conststr.mod: New test.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
8 months agobuild: Move sstream include above safe-ctype.h {PR117771]
Andrew Pinski [Mon, 25 Nov 2024 22:03:27 +0000 (14:03 -0800)] 
build: Move sstream include above safe-ctype.h {PR117771]

sstream in some versions of libstdc++ include locale which might not have been
included yet. safe-ctype.h defines the toupper, tolower, etc. as macros so the
c++ header files needed to be included before hand as comment in system.h says:
/* Include C++ standard headers before "safe-ctype.h" to avoid GCC
   poisoning the ctype macros through safe-ctype.h */

I don't understand how it was working before when memory was included after
safe-ctype.h rather than before. But this makes sstream consistent with the
other C++ headers.

Pushed as obvious after a build for riscv64-elf.

gcc/ChangeLog:

PR target/117771
* system.h: Move the include of sstream above safe-ctype.h.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agosibcall: Check partial != 0 for BLKmode argument
H.J. Lu [Sat, 12 Oct 2024 20:53:14 +0000 (04:53 +0800)] 
sibcall: Check partial != 0 for BLKmode argument

The outgoing stack slot size may be different from the BLKmode argument
size due to parameter alignment.  Check partial != 0 for BLKmode argument
passed on stack.

gcc/

PR middle-end/117098
* calls.cc (store_one_arg): Check partial != 0 for BLKmode argument
passed on stack.

gcc/testsuite/

PR middle-end/117098
* gcc.dg/sibcall-12.c: New test.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
8 months agohppa: Revise TImode aritmetic patterns to support arith11_operands
John David Anglin [Mon, 25 Nov 2024 21:40:29 +0000 (16:40 -0500)] 
hppa: Revise TImode aritmetic patterns to support arith11_operands

2024-11-25  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

PR target/117645
* config/pa/pa.md (addti3): Revise pattern to support
arith11_operands.  Use "R" operand prefix to print least
significant register of TImode register pair.
(addvti3, subti3, subvti3): Likewise.
(negti2, negvti2): Use "R" operand prefix.

8 months ago[PR117105][LRA]: Use unique value reload pseudo for early clobber operand
Vladimir N. Makarov [Mon, 25 Nov 2024 21:09:00 +0000 (16:09 -0500)] 
[PR117105][LRA]: Use unique value reload pseudo for early clobber operand

LRA did not generate insn satisfying insn constraints on the PR
test.  The reason for this is that LRA assigned the same hard reg for
two conflicting reload pseudos.  The two insn reload pseudos are
originated from the same pseudo and LRA tried to optimize as it
assigned the same value for the reload pseudos.  It is an LRA
optimization to minimize reload insns.  The two reload pseudos
conflict as one of them is an early clobber insn operands.  The patch
solves this problem by assigning unique value if the operand is early
clobber one.

gcc/ChangeLog:

PR target/117105
* lra-constraints.cc (get_reload_reg): Create unique value reload
pseudos for early clobbered operands.

gcc/testsuite/ChangeLog:

PR target/117105
* gcc.target/i386/pr117105.c: New test.

8 months agoi386: Generalize x >> 32-y to x >> -y conversion with multiples of 32
Uros Bizjak [Mon, 25 Nov 2024 19:04:38 +0000 (20:04 +0100)] 
i386: Generalize x >> 32-y to x >> -y conversion with multiples of 32

Optimize also cases where immediate value is a multiple of 32 for 32-bit
shifts (or multiple of 64 for 64-bit shifts).

gcc/ChangeLog:

* config/i386/i386.md (*ashl<mode>3_negcnt):
For SImode shifts allow multiples of 32 (or multiples
of 64 for DImode shifts) for immediate operand 3.
(*ashl<mode>3_negcnt_1): Ditto.
(*<insn><mode>3_negcnt): Ditto.
(*<insn><mode>3_negcnt_1): Ditto.

8 months agoRegeernate .opt.urls after nios2 removal
Andrew Pinski [Mon, 25 Nov 2024 18:29:07 +0000 (10:29 -0800)] 
Regeernate .opt.urls after nios2 removal

The index markers changed slightly when nios2 were removed.
This just regenerates the files.

gcc/ChangeLog:

* config/g.opt.urls: Regenerate.
* config/i386/i386.opt.urls: Regenerate.
* config/i386/nto.opt.urls: Regenerate.
* config/nvptx/nvptx.opt.urls: Regenerate.
* config/riscv/riscv.opt.urls: Regenerate.
* config/s390/s390.opt.urls: Regenerate.
* config/sol2.opt.urls: Regenerate.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agonios2: Remove all support for Nios II target.
Sandra Loosemore [Sat, 23 Nov 2024 23:59:13 +0000 (23:59 +0000)] 
nios2: Remove all support for Nios II target.

nios2 target support in GCC was deprecated in GCC 14 as the
architecture has been EOL'ed by the vendor.  This patch removes the
entire port for GCC 15

There are still references to "nios2" in libffi and libgo.  Since those
libraries are imported into the gcc sources from master copies maintained
by other projects, those will need to be addressed elsewhere.

ChangeLog:
* MAINTAINERS: Remove references to nios2.
* configure.ac: Likewise.
* configure: Regenerated.

config/ChangeLog:
* mt-nios2-elf: Deleted.

contrib/ChangeLog:
* config-list.mk: Remove references to Nios II.

gcc/ChangeLog:
* common/config/nios2/*: Delete entire directory.
* config/nios2/*: Delete entire directory.
* config.gcc: Remove references to nios2.
* configure.ac: Likewise.
* doc/extend.texi: Likewise.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* regenerate-opt-urls.py: Likewise.
* config.in: Regenerated.
* configure: Regenerated.

gcc/testsuite/ChangeLog:
* g++.target/nios2/*: Delete entire directory.
* gcc.target/nios2/*: Delete entire directory.
* g++.dg/cpp0x/constexpr-rom.C: Remove refences to nios2.
* g++.old-deja/g++.jason/thunk3.C: Likewise.
* gcc.c-torture/execute/20101011-1.c: Likewise.
* gcc.c-torture/execute/pr47237.c: Likewise.
* gcc.dg/20020312-2.c: Likewise.
* gcc.dg/20021029-1.c: Likewise.
* gcc.dg/debug/btf/btf-datasec-1.c: Likewise.
* gcc.dg/ifcvt-4.c: Likewise.
* gcc.dg/stack-usage-1.c: Likewise.
* gcc.dg/struct-by-value-1.c: Likewise.
* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
* lib/target-supports.exp: Likewise.

libgcc/ChangeLog:
* config/nios2/*: Delete entire directory.
* config.host: Remove refences to nios2.
* unwind-dw2-fde-dip.c: Likewise.

8 months agoFortran: Check IMPURE in BLOCK inside DO CONCURRENT.
Steve Kargl [Mon, 25 Nov 2024 02:26:03 +0000 (18:26 -0800)] 
Fortran: Check IMPURE in BLOCK inside DO CONCURRENT.

PR fortran/117765

gcc/fortran/ChangeLog:

* resolve.cc (check_pure_function): Check the stack to
see if the function is in a nested BLOCK and, if that
block is inside a DO_CONCURRENT, issue an error.

gcc/testsuite/ChangeLog:

* gfortran.dg/impure_fcn_do_concurrent.f90: New test.

8 months agoRISC-V: Ensure vtype for full-register moves [PR117544].
Robin Dapp [Thu, 21 Nov 2024 13:49:53 +0000 (14:49 +0100)] 
RISC-V: Ensure vtype for full-register moves [PR117544].

As discussed in PR117544 the VTYPE register is not preserved across
function calls.  Even though vmv1r-like instructions operate
independently of the actual vtype they still require a valid vtype.  As
we cannot guarantee that the vtype is valid we must make sure to emit a
vsetvl between a function call and a vmv1r.v.

This patch makes the necessary changes by splitting the full-reg-move
insns into patterns that use the vtype register and adding vmov to the
types of instructions requiring a vset.

PR target/117544

gcc/ChangeLog:

* config/riscv/vector.md (*mov<mode>_whole): Split.
(*mov<mode>_fract): Ditto.
(*mov<mode>): Ditto.
(*mov<mode>_vls): Ditto.
(*mov<mode>_reg_whole_vtype): New pattern with vtype use.
(*mov<mode>_fract_vtype): Ditto.
(*mov<mode>_vtype): Ditto.
(*mov<mode>_vls_vtype): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/abi-call-args-4.c: Expect vsetvl.
* gcc.target/riscv/rvv/base/pr117544.c: New test.

8 months agogenemit: Distribute evenly to files [PR111600].
Robin Dapp [Thu, 21 Nov 2024 14:34:37 +0000 (15:34 +0100)] 
genemit: Distribute evenly to files [PR111600].

currently we distribute insn patterns in genemit, partitioning them
by the number of patterns per file.  The first 100 into file 1, the
next 100 into file 2, and so on.  Depending on the patterns this
can lead to files of very uneven sizes.

Similar to the genmatch split, this patch introduces a dynamic
choose_output () which considers the size of the output files
and selects the shortest one for the next pattern.

gcc/ChangeLog:

PR target/111600

* genemit.cc (handle_arg): Use files instead of filenames.
(main): Ditto.
* gensupport.cc (SIZED_BASED_CHUNKS): Define.
(choose_output): New function.
* gensupport.h (choose_output): Declare.

8 months agotarget/116760 - 416.gamess slowdown with SLP
Richard Biener [Mon, 25 Nov 2024 12:32:15 +0000 (13:32 +0100)] 
target/116760 - 416.gamess slowdown with SLP

For the TWOTFF loop vectorization the backend scales constructor
and vector extract cost to make higher VFs less profitable.  This
heuristic currently fails to consider VMAT_STRIDED_SLP which we
now get with single-lane SLP, causing a huge regression in SPEC 2k6
416.gamess for the respective loop nest.

The following fixes this, matching behavior to that of GCC 14 by
treating single-lane VMAT_STRIDED_SLP the same as VMAT_ELEMENTWISE.

PR target/116760
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Scale vec_construct for single-lane VMAT_STRIDED_SLP the
same as VMAT_ELEMENTWISE.
* tree-vect-stmts.cc (vectorizable_store): Pass SLP node
down to costing for vec_to_scalar for VMAT_STRIDED_SLP.

8 months agoAdd extra 64bit SSE vector epilogue in some cases
Richard Biener [Fri, 22 Nov 2024 12:58:08 +0000 (13:58 +0100)] 
Add extra 64bit SSE vector epilogue in some cases

Similar to the X86_TUNE_AVX512_TWO_EPILOGUES tuning which enables
an extra 128bit SSE vector epilouge when doing 512bit AVX512
vectorization in the main loop the following allows a 64bit SSE
vector epilogue to be generated when the previous vector epilogue
still had a vectorization factor of 16 or larger (which usually
means we are operating on char data).

This effectively applies to 256bit and 512bit AVX2/AVX512 main loops,
a 128bit SSE main loop would already get a 64bit SSE vector epilogue.

Together with X86_TUNE_AVX512_TWO_EPILOGUES this means three
vector epilogues for 512bit and two vector epilogues when enabling
256bit vectorization.  I have not added another tunable for this
RFC - suggestions on how to avoid inflation there welcome.

This speeds up 525.x264_r to within 5% of the -mprefer-vector-size=128
speed with -mprefer-vector-size=256 or -mprefer-vector-size=512
(the latter only when -mtune-crtl=avx512_two_epilogues is in effect).

I have not done any further benchmarking, this merely shows the
possibility and looks for guidance on how to expose this to the
uarch tunings or to the user (at all?) if not gating on any uarch
specific tuning.

Note 64bit SSE isn't a native vector size so we rely on emulation
being "complete" (if not epilogue vectorization will only fail, so
it's "safe" in this regard).  With AVX512 ISA available an alternative
is a predicated epilog, but due to possible STLF issues user control
would be required here.

* config/i386/i386.cc (ix86_vector_costs::finish_cost): For an
128bit SSE epilogue request a 64bit SSE epilogue if the 128bit
SSE epilogue VF was 16 or higher.

8 months agotree-optimization/117767 - VMAT_STRIDED_SLP and alignment
Richard Biener [Mon, 25 Nov 2024 08:46:28 +0000 (09:46 +0100)] 
tree-optimization/117767 - VMAT_STRIDED_SLP and alignment

This plugs another hole in alignment checking with VMAT_STRIDED_SLP.
When using an alternate load or store type we have to check whether
that's supported with respect to required vector alignment.

PR tree-optimization/117767
* tree-vect-stmts.cc (vectorizable_store): Check for supported
alignment before using a an alternate store vector type.
(vectorizable_load): Likewise for loads.

* gcc.dg/vect/pr117767.c: New testcase.

8 months agolibsanitizer: Remove -pedantic from AM_CXXFLAGS [PR117732]
Jakub Jelinek [Mon, 25 Nov 2024 08:36:41 +0000 (09:36 +0100)] 
libsanitizer: Remove -pedantic from AM_CXXFLAGS [PR117732]

We aren't the master repository for the sanitizers and clearly upstream
introduces various extensions in the code.
All we care about is whether it builds and works fine with GCC, so
-pedantic flag is of no use to us, only maybe to upstream if they
cared about it (which they clearly don't).

The following patch removes those and fixes some whitespace nits at the same
time.

2024-11-25  Jakub Jelinek  <jakub@redhat.com>

PR sanitizer/117732
* asan/Makefile.am (AM_CXXFLAGS): Remove -pedantic.  Formatting fix.
(asan_files): Formatting fix.
* hwasan/Makefile.am (AM_CXXFLAGS): Remove -pedantic.  Formatting fix.
* interception/Makefile.am (AM_CXXFLAGS): Likewise.
(interception_files): Formatting fix.
* libbacktrace/Makefile.am: Update copyright years.
* lsan/Makefile.am (AM_CXXFLAGS): Remove -pedantic.  Formatting fix.
* sanitizer_common/Makefile.am (AM_CXXFLAGS): Likewise.
(libsanitizer_common_la_DEPENDENCIES): Formatting fix.
* tsan/Makefile.am (AM_CXXFLAGS): Remove -pedantic.  Formatting fix.
* ubsan/Makefile.am (AM_CXXFLAGS): Likewise.
* asan/Makefile.in: Regenerate.
* hwasan/Makefile.in: Regenerate.
* interception/Makefile.in: Regenerate.
* libbacktrace/Makefile.in: Regenerate.
* lsan/Makefile.in: Regenerate.
* sanitizer_common/Makefile.in: Regenerate.
* tsan/Makefile.in: Regenerate.
* ubsan/Makefile.in: Regenerate.

8 months agotestsuite: Fix up various powerpc tests after -std=gnu23 by default switch [PR117663]
Jakub Jelinek [Mon, 25 Nov 2024 08:31:23 +0000 (09:31 +0100)] 
testsuite: Fix up various powerpc tests after -std=gnu23 by default switch [PR117663]

These tests use the K&R function style definitions or pass arguments
to () functions.
It seemed easiest to just use -std=gnu17 for all of those.

2024-11-25  Jakub Jelinek  <jakub@redhat.com>

PR testsuite/117663
* gcc.target/powerpc/pr58673-1.c: Add -std=gnu17 to dg-options.
* gcc.target/powerpc/pr64505.c: Likewise.
* gcc.target/powerpc/pr116170.c: Likewise.
* gcc.target/powerpc/pr58673-2.c: Likewise.
* gcc.target/powerpc/pr64019.c: Likewise.
* gcc.target/powerpc/pr96506-1.c: Likewise.
* gcc.target/powerpc/swaps-stack-protector.c: Likewise.
* gcc.target/powerpc/pr78543.c: Likewise.
* gcc.dg/vect/pr48765.c: Add -std=gnu17 to dg-additional-options.

8 months agotree-optimization/115825 - improve unroll estimates for volatile accesses
Richard Biener [Wed, 10 Jul 2024 10:45:02 +0000 (12:45 +0200)] 
tree-optimization/115825 - improve unroll estimates for volatile accesses

The loop unrolling code assumes that one third of all volatile accesses
can be possibly optimized away which is of course not true.  This leads
to excessive unrolling in some cases.  The following tracks the number
of stmts with side-effects as those are not eliminatable later and
only assumes one third of the other stmts can be further optimized.

This causes some fallout in the testsuite where we rely on unrolling
even when calls are involved.  I have XFAILed g++.dg/warn/Warray-bounds-20.C
but adjusted the others with a #pragma GCC unroll to mimic previous
behavior and retain what the testcase was testing.  I've also filed
PR117671 for the case where the size estimation fails to honor the
stmts we then remove by inserting __builtin_unreachable ().
For gcc.dg/tree-ssa/cunroll-2.c the estimate that the code doesn't
grow is clearly bogus and we have explicit code to reject unrolling
for bodies containing calls so I've adjusted the testcase accordingly.

PR tree-optimization/115825
* tree-ssa-loop-ivcanon.cc (loop_size::not_eliminatable_after_peeling):
New.
(loop_size::last_iteration_not_eliminatable_after_peeling): Likewise.
(tree_estimate_loop_size): Count stmts with side-effects as
not optimistically eliminatable.
(estimated_unrolled_size): Compute the number of stmts that can
be optimistically eliminated by followup transforms.
(try_unroll_loop_completely): Adjust.

* gcc.dg/tree-ssa/cunroll-17.c: New testcase.
* gcc.dg/tree-ssa/cunroll-2.c: Adjust to not expect unrolling.
* gcc.dg/pr94600-1.c: Force unrolling.
* c-c++-common/ubsan/unreachable-3.c: Likewise.
* g++.dg/warn/Warray-bounds-20.C: XFAIL cases we rely on
unrolling loops created by new expressions and not inlined
CTOR invocations.

8 months agoRISC-V: Use dynamic shadow offset
Kito Cheng [Fri, 15 Nov 2024 04:14:55 +0000 (12:14 +0800)] 
RISC-V: Use dynamic shadow offset

Switch to dynamic offset so that we can support Sv39, Sv48, and Sv57 at
the same time without building multiple libasan versions!

[1] https://github.com/llvm/llvm-project/commit/da0c8b275564f814a53a5c19497669ae2d99538d

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_asan_shadow_offset): Use dynamic
offset for RV64.
(riscv_asan_dynamic_shadow_offset_p): New.
(TARGET_ASAN_DYNAMIC_SHADOW_OFFSET_P): New.

gcc/testsuite/ChangeLog:

* g++.dg/asan/asan_test.cc: Update the testcase for dynamic
offset.

8 months agoasan: Support dynamic shadow offset
Kito Cheng [Fri, 15 Nov 2024 04:14:54 +0000 (12:14 +0800)] 
asan: Support dynamic shadow offset

AddressSanitizer has supported dynamic shadow offsets since 2016[1], but
GCC hasn't implemented this yet because targets using dynamic shadow
offsets, such as Fuchsia and iOS, are mostly unsupported in GCC.

However, RISC-V 64 switched to dynamic shadow offsets this year[2] because
virtual memory space support varies across different RISC-V cores, such as
Sv39, Sv48, and Sv57. We realized that the best way to handle this
situation is by using a dynamic shadow offset to obtain the offset at
runtime.

We introduce a new target hook, TARGET_ASAN_DYNAMIC_SHADOW_OFFSET_P, to
determine if the target is using a dynamic shadow offset, so this change
won't affect the static offset path. Additionally, TARGET_ASAN_SHADOW_OFFSET
continues to work even if TARGET_ASAN_DYNAMIC_SHADOW_OFFSET_P is non-zero,
ensuring that KASAN functions as expected.

This patch set has been verified on the Banana Pi F3, currently one of the
most popular RISC-V development boards. All AddressSanitizer-related tests
passed without introducing new regressions.

It was also verified on AArch64 and x86_64 with no regressions in
AddressSanitizer.

[1] https://github.com/llvm/llvm-project/commit/130a190bf08a3d955d9db24dac936159dc049e12
[2] https://github.com/llvm/llvm-project/commit/da0c8b275564f814a53a5c19497669ae2d99538d

gcc/ChangeLog:

* asan.cc (asan_dynamic_shadow_offset_p): New.
(asan_shadow_memory_dynamic_address): New.
(asan_local_shadow_memory_dynamic_address): New.
(get_asan_shadow_memory_dynamic_address_decl): New.
(asan_maybe_insert_dynamic_shadow_at_function_entry): New.
(asan_emit_stack_protection): Support dynamic shadow offset.
(build_shadow_mem_access): Ditto.
* asan.h (asan_maybe_insert_dynamic_shadow_at_function_entry): New.
* doc/tm.texi (TARGET_ASAN_DYNAMIC_SHADOW_OFFSET_P): New.
* doc/tm.texi.in (TARGET_ASAN_DYNAMIC_SHADOW_OFFSET_P): Ditto.
* sanopt.cc (pass_sanopt::execute): Handle dynamic shadow offset.
* target.def (asan_dynamic_shadow_offset_p): New.
* toplev.cc (process_options): Handle dynamic shadow offset.

8 months agoRISC-V: Minimal support for svvptc extension.
Dongyan Chen [Fri, 22 Nov 2024 05:13:46 +0000 (13:13 +0800)] 
RISC-V: Minimal support for svvptc extension.

This patch support svvptc extension[1].
To enable GCC to recognize and process svvptc extension correctly at compile time.

[1] https://github.com/riscv/riscv-svvptc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto.
* config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-44.c: New test.

8 months agoi386/testsuite: Do not append AVX10.2 option for check_effective_target
Haochen Jiang [Fri, 22 Nov 2024 06:32:16 +0000 (14:32 +0800)] 
i386/testsuite: Do not append AVX10.2 option for check_effective_target

When -avx10.2 meet -march with AVX512 enabled, it will report warning
for vector size conflict. The warning will prevent the test to run on
GCC with arch native build on those platforms when
check_effective_target.

Remove AVX10.2 options since we are using inline asm ad it actually do
not need options. It will eliminate the warning.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp (check_effective_target_avx10_2):
Remove AVX10.2 option.
(check_effective_target_avx10_2_512): Ditto.

8 months agopa: Remove pa_section_type_flags
Xi Ruoyao [Sat, 2 Nov 2024 12:20:32 +0000 (20:20 +0800)] 
pa: Remove pa_section_type_flags

It's no longer needed since r15-4842 (when the target-independent code
started to handle the case).

gcc/ChangeLog:

* config/pa/pa.cc (pa_section_type_flags): Remove.
(TARGET_SECTION_TYPE_FLAGS): Remove.

8 months agoAdd target-independent store forwarding avoidance pass
Konstantinos Eleftheriou [Wed, 16 Oct 2024 08:31:39 +0000 (10:31 +0200)] 
Add target-independent store forwarding avoidance pass

This pass detects cases of expensive store forwarding and tries to
avoid them by reordering the stores and using suitable bit insertion
sequences.  For example it can transform this:

     strb    w2, [x1, 1]
     ldr     x0, [x1]      # Expensive store forwarding to larger load.

To:

     ldr     x0, [x1]
     strb    w2, [x1]
     bfi     x0, x2, 0, 8

Assembly like this can appear with bitfields or type punning / unions.
On stress-ng when running the cpu-union microbenchmark the following
speedups have been observed.

  Neoverse-N1:      +29.4%
  Intel Coffeelake: +13.1%
  AMD 5950X:        +17.5%

The transformation is rejected on cases that cause store_bit_field to
generate subreg expressions on different register classes.  Files
avoid-store-forwarding-4.c and avoid-store-forwarding-5.c contain such
cases and have been marked as XFAIL.

Due to biasing of its operands in store_bit_field, there is a special
handling for machines with BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN. The
need for this was exosed by an issue exposed on the H8 architecture,
which uses big-endian ordering, but BITS_BIG_ENDIAN is false. In that
case, the START parameter of store_bit_field needs to be calculated
from the end of the destination register.

gcc/ChangeLog:

* Makefile.in (OBJS): Add avoid-store-forwarding.o.
* common.opt (favoid-store-forwarding): New option.
* common.opt.urls: Regenerate.
* doc/invoke.texi: New param store-forwarding-max-distance.
* doc/passes.texi: Document new pass.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in: Document new pass.
* params.opt (store-forwarding-max-distance): New param.
* passes.def: Add pass_rtl_avoid_store_forwarding before
pass_early_remat.
* target.def (avoid_store_forwarding_p): New DEFHOOK.
* target.h (struct store_fwd_info): Declare.
* targhooks.cc (default_avoid_store_forwarding_p): New function.
* targhooks.h (default_avoid_store_forwarding_p): Declare.
* tree-pass.h (make_pass_rtl_avoid_store_forwarding): Declare.
* avoid-store-forwarding.cc: New file.
* avoid-store-forwarding.h: New file.
* timevar.def (TV_AVOID_STORE_FORWARDING): New timevar.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/avoid-store-forwarding-1.c: New test.
* gcc.target/aarch64/avoid-store-forwarding-2.c: New test.
* gcc.target/aarch64/avoid-store-forwarding-3.c: New test.
* gcc.target/aarch64/avoid-store-forwarding-4.c: New test.
* gcc.target/aarch64/avoid-store-forwarding-5.c: New test.
* gcc.target/x86_64/abi/callabi/avoid-store-forwarding-1.c: New test.
* gcc.target/x86_64/abi/callabi/avoid-store-forwarding-2.c: New test.

Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
8 months agoFix uninitialized operands[2] in vec_unpacks_hi_v4sf.
liuhongt [Fri, 22 Nov 2024 07:57:38 +0000 (23:57 -0800)] 
Fix uninitialized operands[2] in vec_unpacks_hi_v4sf.

It could cause weired spill in RA when register pressure is high.

gcc/ChangeLog:

PR target/117562
* config/i386/sse.md (vec_unpacks_hi_v4sf): Initialize
operands[2] with CONST0_RTX.

8 months agoDaily bump.
GCC Administrator [Mon, 25 Nov 2024 00:18:18 +0000 (00:18 +0000)] 
Daily bump.

8 months agoipa: Move individual jump function copying to a separate function
Martin Jambor [Sun, 24 Nov 2024 22:03:43 +0000 (23:03 +0100)] 
ipa: Move individual jump function copying to a separate function

When reviewing various IPA bits and pieces I have falsely assumed
that jump function duplication misses copying important bits because
it relies on vec_safe_copy-ing all data in the vector of jump
functions and then just fixes up the few fields it needs to.

Perhaps more importantly, we do want a function to copy one individual
jump function to form jump functions for planned call-graph edges that
model transfer of control to OpenMP outlined regions through calls to
gomp functions.

Therefore, this patch introduces such function and makes
ipa_edge_args_sum_t::duplicate just allocate the new vectors and then
uses the new function to copy the data.

gcc/ChangeLog:

2024-11-01  Martin Jambor  <mjambor@suse.cz>

* ipa-prop.cc (ipa_duplicate_jump_function): New function.
(ipa_edge_args_sum_t::duplicate): Move individual jump function
copying to ipa_duplicate_jump_function.

8 months agotestsuite/x86: Add -mfpmath=sse to add_options_for_float16
Uros Bizjak [Sun, 24 Nov 2024 21:18:31 +0000 (22:18 +0100)] 
testsuite/x86: Add -mfpmath=sse to add_options_for_float16

Add -mfpmath=sse to add_options_for_float16 to avoid error:
'-fexcess-precision=16' is not compatible with '-mfpmath=387'
when compiling gcc.dg/tree-ssa/pow_fold_1.c.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp (add_options_for_float16): Add -mpfpmath=sse.

8 months agoi386: x86 can use x >> -y for x >> 32-y [PR36503]
Uros Bizjak [Sun, 24 Nov 2024 21:00:18 +0000 (22:00 +0100)] 
i386: x86 can use x >> -y for x >> 32-y [PR36503]

x86 targets mask 32-bit shifts with a 5-bit mask (and 64-bit with 6-bit mask),
so they can use x >> -y instead of x >> 32-y.  This form is very common in
bitstream readers, where it's used to read the top N bits from a word.

The optimization converts:

        movl    $32, %ecx
        subl    %esi, %ecx
        sall    %cl, %eax

to:

        negl    %ecx
        sall    %cl, %eax

PR target/36503

gcc/ChangeLog:

* config/i386/i386.md (*ashl<mode>3_negcnt):
New define_insn_and_split pattern.
(*ashl<mode>3_negcnt_1): Ditto.
(*<insn><mode>3_negcnt): Ditto.
(*<insn><mode>3_negcnt_1): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr36503-1.c: New test.
* gcc.target/i386/pr36503-2.c: New test.

8 months agoopt.url: Regenerate the .opt.urls files
Andrew Pinski [Sun, 24 Nov 2024 19:58:54 +0000 (11:58 -0800)] 
opt.url: Regenerate the .opt.urls files

Just regenerated them after the addition of msplit-bit-shift avr option.

Pushed as obvious.

gcc/ChangeLog:

* config/avr/avr.opt.urls: Regenerate.
* config/g.opt.urls: Regenerate.
* config/i386/nto.opt.urls: Regenerate.
* config/riscv/riscv.opt.urls: Regenerate.
* config/rx/rx.opt.urls: Regenerate.
* config/sol2.opt.urls: Regenerate.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agogimplefe: Fix handling of ')'/'}' after a parse error [PR117741]
Andrew Pinski [Sat, 23 Nov 2024 21:42:47 +0000 (13:42 -0800)] 
gimplefe: Fix handling of ')'/'}' after a parse error [PR117741]

The problem here is c_parser_skip_until_found stops at a closing nesting
delimiter without consuming it. So if we don't consume it in
c_parser_gimple_compound_statement, we would go into an infinite loop. The C
parser similar code in c_parser_statement_after_labels to handle this specific
case too.

PR c/117741

gcc/c/ChangeLog:

* gimple-parser.cc (c_parser_gimple_compound_statement): Handle
CPP_CLOSE_PAREN/CPP_CLOSE_SQUARE with an error and skipping the token.

gcc/testsuite/ChangeLog:

* gcc.dg/gimplefe-54.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
8 months agoFix vectorization regressions on the SPARC
Eric Botcazou [Sun, 24 Nov 2024 19:23:34 +0000 (20:23 +0100)] 
Fix vectorization regressions on the SPARC

This fixes the vectorization regressions present on the SPARC by switching
from vcond[u] patterns to vec_cmp[u] + vcond_mask_ patterns.  While I was
at it, I merged the patterns for V4HI/V2SI and V8QI enabled with VIS 3/VIS 4
to follow the model of those enabled with VIS 4B, and standardized all the
mnemonics to the version documented in the Oracle SPARC architecture 2015.

gcc/
PR target/117715
* config/sparc/sparc-protos.h (sparc_expand_vcond): Rename to...
(sparc_expand_vcond_mask): ...this.
* config/sparc/sparc.cc (TARGET_VECTORIZE_GET_MASK_MODE): Define.
(sparc_vis_init_builtins): Adjust the CODE_FOR_* identifiers.
(sparc_get_mask_mode): New function.
(sparc_expand_vcond): Rename to...
(sparc_expand_vcond_mask): ...this and adjust.
* config/sparc/sparc.md (unspec): Remove UNSPEC_FCMP & UNSPEC_FUCMP
and rename UNSPEC_FPUCMPSHL into UNSPEC_FPCMPUSHL.
(fcmp<gcond:code><GCM:gcm_name><P:mode>_vis): Merge into...
(fpcmp<gcond:code>8<P:mode>_vis): Merge into...
(fpcmp<fpcmpcond:code><FPCMP:vbits><P:mode>_vis): ...this.
(fucmp<gcond:code>8<P:mode>_vis): Merge into...
(fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis): Merge into...
(fpcmpu<fpcmpucond:signed_code><FPCMP:vbits><P:mode>_vis): ...this.
(vec_cmp<FPCMP:mode><P:mode>): New expander.
(vec_cmpu<FPCMP:mode><P:mode>): Likewise.
(vcond<GCM:mode><GCM:mode>): Delete.
(vcondv8qiv8qi): Likewise.
(vcondu<GCM:mode><GCM:mode>): Likewise.
(vconduv8qiv8qi): Likewise.
(vcond_mask_<FPCMP:mode><P:mode>): New expander.
(fpcmp<fpcscond:code><FPCSMODE:vbits><P:mode>shl): Adjust.
(fpcmpu<fpcsucond:code><FPCSMODE:vbits><P:mode>shl): Likewise.
(fpcmpde<FPCSMODE:vbits><P:mode>shl): Likewise.
(fpcmpur<FPCSMODE:vbits><P:mode>shl): Likewise.
* doc/md.texi (vcond_mask_len_): Fix pasto.

gcc/testsuite/
* gcc.target/sparc/20230328-1.c: Adjust to new mnemonics.
* gcc.target/sparc/20230328-4.c: Likewise.
* gcc.target/sparc/fcmp.c: Likewise.
* gcc.target/sparc/fucmp.c: Likewise.

8 months agoAdjust error message for initialized variable in .bss
Eric Botcazou [Sun, 24 Nov 2024 14:15:54 +0000 (15:15 +0100)] 
Adjust error message for initialized variable in .bss

The current message does not make sense with -fno-zero-initialized-in-bss.

gcc/
* doc/invoke.texi (-fno-zero-initialized-in-bss): Adjust for Ada.
* varasm.cc (get_variable_section): Adjust the error message for an
initialized variable in .bss to -fno-zero-initialized-in-bss.

gcc/testsuite/
* gnat.dg/specs/bss1.ads: New test.

8 months agoFortran: Correct name of testcase [PR84869]
Paul Thomas [Sun, 24 Nov 2024 14:01:21 +0000 (14:01 +0000)] 
Fortran: Correct name of testcase [PR84869]

2024-11-24  Paul Thomas  <pault@gcc.gnu.org>

gcc/testsuite/
PR fortran/84869
* gfortran.dg/pr84869.f90: Copy of test below with number
   corrected.
* gfortran.dg/pr85869.f90: deleted.

8 months agoFortran: Fix segfault in allocation of unlimited poly array [PR85869]
Paul Thomas [Sun, 24 Nov 2024 12:01:32 +0000 (12:01 +0000)] 
Fortran: Fix segfault in allocation of unlimited poly array [PR85869]

2024-11-24  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran/ChangeLog

PR fortran/85869
* trans-expr.cc (trans_class_vptr_len_assignment): To access
the '_len' field, re must be unlimited polymorphic.

gcc/testsuite/
PR fortran/85869
* gfortran.dg/pr85869.f90: Comment out test of component refs.

8 months agoFortran: Fix non_overridable typebound proc problems [PR84674/117730].
Paul Thomas [Sun, 24 Nov 2024 08:50:58 +0000 (08:50 +0000)] 
Fortran: Fix non_overridable typebound proc problems [PR84674/117730].

2024-11-24  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran/ChangeLog

PR fortran/117730
* class.cc (add_proc_comp): Only reject a non_overridable if it
has no overridden procedure and the component is already
present in the vtype.
PR fortran/84674
* resolve.cc (resolve_fl_derived): Do not build a vtable for a
derived type extension that is completely empty.

gcc/testsuite/ChangeLog

PR fortran/117730
* gfortran.dg/pr117730_a.f90: New test.
* gfortran.dg/pr117730_b.f90: New test.

PR fortran/84674
* gfortran.dg/pr84674.f90: New test.

8 months agoRISC-V: Refine the vector stride load/store testcases
Pan Li [Thu, 21 Nov 2024 06:30:49 +0000 (14:30 +0800)] 
RISC-V: Refine the vector stride load/store testcases

The rtl expand dump for IFN check of stride load/store testcase is
different between O2 and O3.  It it reasonable to leverage target
no-opts/any-opts to filte out, instead of the xfail.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Take
the target any-ops instead of xfail.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Refactor the test files for all other vector SAT ALU
Pan Li [Thu, 21 Nov 2024 06:30:48 +0000 (14:30 +0800)] 
RISC-V: Refactor the test files for all other vector SAT ALU

This patch would like to refactor the all the other testcases of vector
SAT ALU after move to rvv/autovec/sat folder.  Includes:

* Refine the include header files.
* Remove unnecessary optimization options.
* Reconcile the dump check based on option no-opts and/or any-opts.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Refine
the include file, remove unnecessary options and reconcile the
dump check based on options.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto.
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Removed.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Rearrange the test files for all other vector SAT ALU [NFC]
Pan Li [Thu, 21 Nov 2024 06:30:47 +0000 (14:30 +0800)] 
RISC-V: Rearrange the test files for all other vector SAT ALU [NFC]

Move all other test files of SAT ALU to riscv/rvv/autovec/sat/.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-1-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-1-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-1-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-1-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-3-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-4-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-1-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-1-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-1-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-1-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-3-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i64.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-4-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvv_run.h: Removed.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvx_run.h: Removed.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx_run.h: Removed.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Removed.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h: Removed.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_unary_vv_run.h: Removed.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Refactor the testcases for vector SAT_TRUNC
Pan Li [Thu, 21 Nov 2024 06:30:46 +0000 (14:30 +0800)] 
RISC-V: Refactor the testcases for vector SAT_TRUNC

This patch would like to refactor the testcases of vector SAT_TRUNC
after move to rvv/autovec/sat folder.  Includes:

* Refine the include header files.
* Remove unnecessary optimization options.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c:
Refine the include file and remove unnecessary optimization options.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c: Ditto

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Rearrange the test files for vector SAT_TRUNC [NFC]
Pan Li [Thu, 21 Nov 2024 06:30:45 +0000 (14:30 +0800)] 
RISC-V: Rearrange the test files for vector SAT_TRUNC [NFC]

The test files of vector SAT_TRUNC only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}.  For example,
test form 3 for uint32_t SAT_TRUNC will have -3-u32.c for asm check
and -run-3-u32.c for the run test.

Meanwhile, moved all related test files to riscv/rvv/autovec/sat/.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: Merge the
same file name under autovec/unop.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-21.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-22.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-24.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-23.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-18.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-19.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-20.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-17.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_unary_vv_run.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Refactor the testcases for vector SAT_SUB
Pan Li [Thu, 21 Nov 2024 06:30:44 +0000 (14:30 +0800)] 
RISC-V: Refactor the testcases for vector SAT_SUB

This patch would like to refactor the testcases of vector SAT_SUB
after move to rvv/autovec/sat folder.  Includes:

* Refine the include header files.
* Remove unnecessary optimization options.
* Adjust dg-final by any-opts and/or no-opts if the rtl dump changes
  on different optimization options (like O2, O3).

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c:
Refactor the test case for include, unnecessary option and
target on opts.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoRISC-V: Rearrange the test files for vector SAT_SUB [NFC]
Pan Li [Thu, 21 Nov 2024 06:30:43 +0000 (14:30 +0800)] 
RISC-V: Rearrange the test files for vector SAT_SUB [NFC]

The test files of vector SAT_SUB only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}.  For example,
test form 3 for uint32_t SAT_SUB will have -3-u32.c for asm check and
-run-3-u32.c for the run test.

Meanwhile, moved all related test files to riscv/rvv/autovec/sat/.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-run-1-u8.c: ...here.

Signed-off-by: Pan Li <pan2.li@intel.com>
8 months agoDaily bump.
GCC Administrator [Sun, 24 Nov 2024 00:18:09 +0000 (00:18 +0000)] 
Daily bump.

8 months agoc-family: Regenerate c.opt.urls
Jakub Jelinek [Sat, 23 Nov 2024 21:06:23 +0000 (22:06 +0100)] 
c-family: Regenerate c.opt.urls

2024-11-23  Jakub Jelinek  <jakub@redhat.com>

* c.opt.urls: Regenerate.

8 months agolibcpp: Fix ICE lexing invalid raw string in a deferred pragma [PR117118]
Lewis Hyatt [Mon, 14 Oct 2024 21:59:46 +0000 (17:59 -0400)] 
libcpp: Fix ICE lexing invalid raw string in a deferred pragma [PR117118]

The PR shows that we ICE after lexing an invalid unterminated raw string,
because lex_raw_string() pops the main buffer unexpectedly. Resolve by
handling this case the same way as for other directives.

libcpp/ChangeLog:
PR preprocessor/117118
* lex.cc (lex_raw_string): Treat an unterminated raw string the same
way for a deferred pragma as is done for other directives.

gcc/testsuite/ChangeLog:
PR preprocessor/117118
* c-c++-common/raw-string-directive-3.c: New test.
* c-c++-common/raw-string-directive-4.c: New test.

8 months agogimple: Handle tail padding when computing gimple_ops_offset
Lewis Hyatt [Tue, 29 Oct 2024 20:57:12 +0000 (16:57 -0400)] 
gimple: Handle tail padding when computing gimple_ops_offset

The array gimple_ops_offset_[], which is used to find the trailing op[]
array for a given gimple struct, is computed assuming that op[] will be
found at sizeof(tree) bytes away from the end of the struct. This is only
correct if the alignment requirement of a pointer is the same as the
alignment requirement of the struct, otherwise there will be padding bytes
that invalidate the calculation. On 64-bit platforms, this generally works
fine because a pointer has 8-byte alignment and none of the structs make use
of more than that. On 32-bit platforms, it also currently works fine because
there are no 64-bit integers in the gimple structs. There are 32-bit
platforms (e.g. sparc) on which a pointer has 4-byte alignment and a
uint64_t has 8-byte alignment. On such platforms, adding a uint64_t to the
gimple structs (as will take place when location_t is changed to be 64-bit)
causes gimple_ops_offset_ to be 4 bytes too large.

It would be nice to use offsetof() to compute the offset exactly, but
offsetof() is not guaranteed to work for these types, because they use
inheritance and so are not standard layout types. This patch attempts to
detect the presence of tail padding by detecting when such padding is reused
by inheritance; the padding should generally be reused for the same reason
that offsetof() is not available, namely that all the relevant types use
inheritance. One could envision systems on which this fix does not go far
enough (e.g., if the ABI forbids reuse of tail padding), but it makes things
better without affecting anything that currently works.

gcc/ChangeLog:

* gimple.cc (get_tail_padding_adjustment): New function.
(DEFGSSTRUCT): Adjust the computation of gimple_ops_offset_ to be
correct in the presence of tail padding.

8 months agoSupport for 64-bit location_t: C++ modules parts
Lewis Hyatt [Fri, 25 Oct 2024 14:18:12 +0000 (10:18 -0400)] 
Support for 64-bit location_t: C++ modules parts

The modules implementation is necessarily sensitive to the internal workings
of class line_map, and so it needed changes in order to handle a 64-bit
location_t. The changes mostly boil down to supporting that in the debug
dumping routines (which is accomplished by using a new custom code %K for
that purpose), and supporting that when streaming in and out from the
module (which is accomplished by using a new loc() function to go along with
existing abstractions like u() or z() for streaming in and out different
data types).

gcc/cp/ChangeLog:

* module.cc (bytes_out::loc): New function.
(bytes_in::loc): New function.
(struct span): Change int fields to location_diff_t.
(range_t): Change from "unsigned int" to "line_map_uint_t".
(struct ord_loc_info): Likewise.
(struct macro_loc_info): Likewise.
(class module_state): Likewise.
(dumper::operator()): Add new code 'K' for dumping a location_t.
(loc_spans::init): Use %K instead of %u for location_t dumps.
(loc_spans::open): Likewise.
(loc_spans::close): Likewise. Adjust bitwise expressions to support
64-bit location_t as well.
(struct module_state_config): Change ordinary_locs and macro_locs
from "unsigned int" to "line_map_uint_t".  Reorder fields to improve
packing.  Rather than changing the constructor initializer list to
match the new order, switch to NSDMI instead.
(module_state::note_location): Adjust to support 64-bit location_t.
(module_state::write_location): Use %K instead of %u for location_t
dumps. Use loc() instead of u() for streaming location_t.
(module_state::read_location): Likewise.
(module_state::write_ordinary_maps): Likewise.
(module_state::write_macro_maps): Likewise.
(module_state::write_config): Likewise.
(module_state::read_config): Likewise.
(module_state::write_prepare_maps): Use %K instead of %u for
location_t dumps. Adjust variable types and bitwise expressions to
support 64-bit location_t.
(module_state::read_ordinary_maps): Likewise.
(module_state::read_macro_maps): Likewise.
(preprocess_module): Adjust data types to support 64-bit number of
line maps.

8 months agoSupport for 64-bit location_t: Analyzer parts
Lewis Hyatt [Mon, 28 Oct 2024 16:55:24 +0000 (12:55 -0400)] 
Support for 64-bit location_t: Analyzer parts

The analyzer occasionally prints internal location_t values for debugging;
adjust those parts so they will work if location_t is 64-bit. For
simplicity, to avoid hassling with the printf format string, just convert to
(unsigned long long) in either case.

gcc/analyzer/ChangeLog:

* checker-event.cc (checker_event::dump): Support printing either
32- or 64-bit location_t values.
* checker-path.cc (checker_path::inject_any_inlined_call_events):
Likewise.

8 months agoSupport for 64-bit location_t: Frontend parts
Lewis Hyatt [Mon, 28 Oct 2024 16:52:23 +0000 (12:52 -0400)] 
Support for 64-bit location_t: Frontend parts

The C/C++ frontend code contains a couple instances where a callback
receiving a "location_t" argument is prototyped to take "unsigned int"
instead. This will make a difference once location_t can be configured to a
different type, so adjust that now.

Also remove a comment about -flarge-source-files, which will be removed
shortly.

gcc/c-family/ChangeLog:

* c-indentation.cc (should_warn_for_misleading_indentation): Remove
comment about -flarge-source-files.
* c-lex.cc (cb_ident): Change "unsigned int" argument to type
"location_t".
(cb_def_pragma): Likewise.
(cb_define): Likewise.
(cb_undef): Likewise.

8 months agolibcpp: Fix potential unaligned access in cpp_buffer
Lewis Hyatt [Mon, 28 Oct 2024 21:57:41 +0000 (17:57 -0400)] 
libcpp: Fix potential unaligned access in cpp_buffer

libcpp makes use of the cpp_buffer pfile->a_buff to store things while it is
handling macros. It uses it to store pointers (cpp_hashnode*, for macro
arguments) and cpp_macro objects. This works fine because a cpp_hashnode*
and a cpp_macro have the same alignment requirement on either 32-bit or
64-bit systems (namely, the same alignment as a pointer.)

When 64-bit location_t is enabled on a 32-bit sytem, the alignment
requirement may cease to be the same, because the alignment requirement of a
cpp_macro object changes to that of a uint64_t, which be larger than that of
a pointer. It's not the case for x86 32-bit, but for example, on sparc, a
pointer has 4-byte alignment while a uint64_t has 8. In that case,
intermixing the two within the same cpp_buffer leads to a misaligned
access. The code path that triggers this is the one in _cpp_commit_buff in
which a hash table with its own allocator (i.e. ggc) is not being used, so
it doesn't happen within the compiler itself, but it happens in the other
libcpp clients, such as genmatch.

Fix that up by ensuring _cpp_commit_buff commits a fully aligned chunk of the
buffer, so it's ready for anything it may be used for next.

Also modify CPP_ALIGN so that it guarantees to return an alignment at least
the size of location_t. Currently it returns the max of a pointer and a
double. I am not aware of any platform where a double may have smaller
alignment than a uint64_t, but it does not hurt to add location_t here to be
sure.

libcpp/ChangeLog:

* lex.cc (_cpp_commit_buff): Make sure that the buffer is properly
aligned for the next allocation.
* internal.h (struct dummy): Make sure alignment is large enough for
a location_t, just in case.