H.J. Lu [Sat, 3 Feb 2024 22:32:17 +0000 (14:32 -0800)]
x86-64: Add R_X86_64_CODE_6_GOTTPOFF
For
add %reg1, name@gottpoff(%rip), %reg2
and
add name@gottpoff(%rip), %reg1, %reg2
add
#define R_X86_64_CODE_6_GOTTPOFF 50
if the instruction starts at 6 bytes before the relocation offset.
They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to
add $name@tpoff, %reg1, %reg2
Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate
R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX,
R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and
R_X86_64_CODE_6_GOTTPOFF.
NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in
md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this
stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF
or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix.
Alan Modra [Thu, 8 Feb 2024 20:34:22 +0000 (07:04 +1030)]
PR31208, strip can break ELF alignment requirements
In https://sourceware.org/pipermail/binutils/2007-August/053261.html
(git commit 3dea8fca8b86) I disabled a then new linker feature that
removed empty PT_LOAD headers in cases where a user specified program
headers, and for objcopy. This can be a problem for objcopy/strip and
since objcopy operates on sections, any part of a PT_LOAD loading file
contents not covered by a section will be omitted anyway.
PR 31208
* elf.c (_bfd_elf_map_sections_to_segments): Pass remove_empty_load
as true to elf_modify_segment_map for objcopy/strip.
PR 31283 windmc: Parse input correctly on big endian hosts
On big endian hosts (eg. s390x) the windmc tool fails to parse even
trivial files:
$ cat test.mc
;
$ ./binutils/windmc ./test.mc
In test.mc at line 1: parser: syntax error.
In test.mc at line 1: fatal: syntax error.
The tool starts by reading the input as Windows CP1252 and then
converting it internally into an array of UTF-16LE, which it then
processes as an array of unsigned short (typedef unichar).
There are lots of ways this is wrong, but in the specific case of big
endian machines the little endian pairs of bytes are byte-swapped.
For example, the ';' character in the input above is first converted
to UTF16-LE byte sequence { 0x3b, 0x00 }, which is then cast to
unsigned short. On a big endian machine the first unichar appears to
be 0x3b00. The lexer is unable to recognize this as the comment
character ((unichar)';') and so parsing fails.
The simple fix is to convert the input to UTF-16BE on big endian
machines (and do the reverse conversion when writing the output).
Fixes: https://sourceware.org/bugzilla/show_bug.cgi?id=31283 Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
(cherry picked from commit 3f8f9745c75b333515f399fc2908ede2ed8014e9)
Xi Ruoyao [Fri, 2 Feb 2024 13:00:58 +0000 (21:00 +0800)]
LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtab
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a
TLS symbol and we should set its type to TLS in the symtab. Otherwise
when building Perl with gcc-14 -flto, we get:
/usr/bin/ld: PL_current_context: TLS definition in
./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference
in ./miniperl.ltrans1.ltrans.o
Unfortunately this was undetected before Binutils-2.42 release because
GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a
TLS LE definition and its reference in two different translation units.
So this fix should be backported to Binutils-2.42 branch too.
Instructions with length > 15 bytes are always invalid. It is quite easy
to generate invalid instructions with APX now. We should issue an error
when instruction length exceeds the limit of 15 bytes.
PR gas/31323
* config/tc-i386.c (output_insn): Issue an error when instruction
length exceeds the limit of 15 bytes.
* testsuite/gas/i386/oversized16.l: Updated.
* testsuite/gas/i386/oversized64.l: Likewise.
* testsuite/gas/i386/x86-64-apx-inval.l: New file.
* testsuite/gas/i386/x86-64-apx-inval.s: Likewise.
Georg-Johann Lay [Wed, 31 Jan 2024 11:24:22 +0000 (11:24 +0000)]
PR31124: Addendum: Remove PROVIDE of __flmap_init_label, __flmap.
Supply these symbols as computed by the linker scripts, even when there are weak definitions.
PR 31124
* scripttempl/avr.sc (__flmap, __flmap_init_label): Remove PROVIDE.
mengqinggang [Fri, 26 Jan 2024 10:50:57 +0000 (10:50 +0000)]
Backport commits 969f5c0e1 (LoongArch: gas: Add support for s9 register) and a0aa6f4ab (LoongArch: ld: Add support for TLS LE symbol with addend) to 2.42 branch.
Restructure the architecture extensions table, add a new table for architecture
version dependencies, add missing architecture extensions, and improve some
extension descriptions.
mengqinggang [Thu, 18 Jan 2024 11:03:11 +0000 (19:03 +0800)]
LoongArch: gas: Start a new frag after instructions that can be relaxed
For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20}
relocations, start a new frag to get correct eh_frame Call Frame Information
FDE DW_CFA_advance_loc info.
mengqinggang [Sun, 1 Oct 2023 07:29:44 +0000 (15:29 +0800)]
LoongArch: gas: Don't define LoongArch .align
Gcc may generate "\t.align\t%d,54525952,4\n" before commit b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object
file, we call s_align_ptwo (-4). It result in alignment padding must be a
multiple of 4 if .align has second parameter.
Xi Ruoyao [Fri, 19 Jan 2024 16:38:24 +0000 (00:38 +0800)]
LoongArch: Fix some test failures about TLS desc and TLS relaxation
There are two issues causing 11 test failures:
1. The TLS desc tests are matching the entire disassemble of a linked
executable. But if ld is configured --enable-default-hash-style=gnu
(note that most modern distros use this option), the layout of the
linked executables will be different and the immediate operands in
the linked executables will also be different. So we add
"--hash-style=both" for these tests to cancel the effect of
--enable-default-hash-style=gnu, like [x86_64 mark-plt tests].
2. By default objdump disassemble uses [pseudo-instructions] so "addi.w"
is outputed as "li.w", causing mismatches in TLS relaxation tests.
We can turn off the pseudo-instruction usage in objdump using "-M
no-aliases" to fix them.
Andrew Carlotti [Wed, 17 Jan 2024 12:37:15 +0000 (12:37 +0000)]
aarch64: Include +predres2 in -march=armv8.9-a
This matches the dependencies in the architecture, in LLVM, and even in the
original Binutils commit message that mistakenly included it only in armv9.4-a.
Jan Beulich [Mon, 22 Jan 2024 07:52:30 +0000 (08:52 +0100)]
x86/APX: also amend the PUSH2/POP2 testcase
Commit f530d5f1bab6 ("Update x86/APX: VROUND{P,S}{S,D} can generally be
encoded") took care of only half of the remaining issue. Add #pass here
as well.
Fix 31252 gprofng causes testsuite parallel jobs fail
Before running our tests, we made a fake installation into ./tmpdir.
This installation changes libopcodes.la in the build area.
Gas testing may fail if gas and gprofng tests are run in parallel.
I create a script to run gprofng. Inside this script, LD_LIBRARY_PATH,
GPROFNG_SYSCONFDIR are set.
putenv_libcollector_ld_misc() first uses $GPROFNG_PRELOAD_LIBDIRS to create
directories for SP_COLLECTOR_LIBRARY_PATH ($SP_COLLECTOR_LIBRARY_PATH is used
to set up LD_PRELOAD).
gprofng/ChangeLog
2024-01-19 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
PR gprofng/31252
PR gprofng/30808
* src/envsets.cc (putenv_libcollector_ld_misc): Use
$GPROFNG_PRELOAD_LIBDIRS first to build SP_COLLECTOR_LIBRARY_PATH.
* testsuite/config/default.exp: Create a script to run gprofng.
* testsuite/lib/display-lib.exp: Fix typo.
Jan Beulich [Fri, 19 Jan 2024 09:18:32 +0000 (10:18 +0100)]
x86/APX: VROUND{P,S}{S,D} can generally be encoded
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
Jan Beulich [Fri, 19 Jan 2024 09:17:44 +0000 (10:17 +0100)]
x86/APX: be consistent with insn suffixes
When there's a suitably disambiguating register operand, suffixes are
generally omitted (unless in suffix-always mode). All NDD insns have a
suitable register operand, so they shouldn't have suffixes by default.
Xi Ruoyao [Tue, 16 Jan 2024 07:00:16 +0000 (15:00 +0800)]
LoongArch: Adapt R_LARCH_{PCALA,GOT,TLS_IE,TLS_DESC}64_* handling per psABI v2.30
In LoongArch psABI v2.30, an offset (-8 for LO20 and -12 for HI12)
should be applied on PC for these reloc types to avoid wrong relocation
when the instruction sequence crosses a page boundary.
The lld linker has already adapted the change. Make it for the bfd
linker too.
Alan Modra [Tue, 16 Jan 2024 00:36:23 +0000 (11:06 +1030)]
PR30824 internal error with -z pack-relative-relocs
This corrects a counting problem, where prior to relocate_section relr
encoded relative relocs were allowed when it was known they were on
even boundaries, but relocate_section can only put relative relocs
(non-relr) on eight byte boundaries.
PR 30824
* elf64-ppc.c (RELR_ALIGN): Define, use throughout.
(maybe_relr): New function, use throughout.
aarch64: rcpc3: add support in general_constraint_met_p
Given the introduction of the new address operand types for rcpc3
instructions, this patch adds the necessary logic to teach
`general_constraint_met_p` how to proper handle these.
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
aarch64: rcpc3: Define address operand fields and inserter/extractors
Beyond the need to encode any registers involved in data transfer and
the address base register for load/stores, it is necessary to specify
the data register addressing mode and whether the address register is
to be pre/post-indexed, whereby loads may be post-indexed and stores
pre-indexed with write-back.
The use of a single bit to specify both the indexing mode and indexing
value requires a novel function be written to accommodate this for
address operand insertion in assembly and another for extraction in
disassembly, along with the definition of two insn fields for use with
these instructions.
projects / thirdparty / binutils-gdb.git / log
