Jakub Jelinek [Wed, 24 Oct 2012 09:08:56 +0000 (11:08 +0200)]
re PR debug/54828 (ICE in based_loc_descr at dwarf2out.c:10560 with -g -O0)
PR debug/54828
* gimple.h (is_gimple_sizepos): New inline function.
* gimplify.c (gimplify_one_sizepos): Use it. Remove useless
final assignment to expr variable.
* tree.c (RETURN_TRUE_IF_VAR): Return true also if
!TYPE_SIZES_GIMPLIFIED (type) and _t is going to be gimplified
into a local temporary.
David S. Miller [Wed, 24 Oct 2012 05:59:27 +0000 (05:59 +0000)]
Use define_memory_constraint on sparc when necessary.
* config/sparc/constraints.md ("T", "W"): Change
definitions to use define_memory_constraint. Do not match
'reg'.
* config/sparc/sparc.c (memory_ok_for_ldd): Remove all non-MEM
handling code, update comment.
Jeff Law [Tue, 23 Oct 2012 20:33:49 +0000 (14:33 -0600)]
re PR tree-optimization/54985 (dom optimization erroneous remove conditional goto.)
PR tree-optimization/54985
* tree-ssa-threadedge.c (cond_arg_set_in_bb): New function
* extracted
from thread_across_edge.
(thread_across_edge): Use it in all cases where we might thread
across a back edge.
expmed.c (store_split_bit_field): Update the calls to extract_fixed_bit_field.
gcc/
* expmed.c (store_split_bit_field): Update the calls to
extract_fixed_bit_field. In the big-endian case, always
use the mode of OP0 to count the number of significant bits.
(extract_bit_field_1): Remove unit, offset, bitpos and
byte_offset from the outermost scope. Express conditions in terms
of bitnum rather than offset, bitpos and byte_offset. Move the
computation of MODE1 to the block that needs it. Use MODE unless
the TMODE-based mode_for_size calculation succeeds. Split the
plain move cases into two, one for memory accesses and one for
register accesses. Generalize the memory case, freeing it from
the old register-based endian checks. Move the INT_MODE calculation
above the code that needs it. Use simplify_gen_subreg to handle
multiword OP0s. If the field still spans several words, pass it
directly to extract_split_bit_field. Assume after that point
that both targets and register sources fit within a word.
Replace x-prefixed variables with non-prefixed forms.
Compute the bitpos for ext(z)v register operands directly in the
chosen unit size, rather than going through an intermediate
BITS_PER_WORD unit size. Simplify the containment check
used when forcing OP0 into a register. Update the call to
extract_fixed_bit_field.
(extract_fixed_bit_field): Replace the bitpos and offset parameters
with a single bitnum parameter, of the same form as extract_bit_field.
Assume that OP0 contains the full field. Simplify the memory offset
calculation and containment check for volatile bitfields. Make the
offset explicit when volatile bitfields force a misaligned access.
Remove WARNED and fix long lines. Assert that the processed OP0
has an integral mode.
(store_split_bit_field): Update the call to store_fixed_bit_field.
gcc/
* expmed.c (lowpart_bit_field_p): New function.
(store_bit_field_1): Remove unit, offset, bitpos and byte_offset
from the outermost scope. Express conditions in terms of bitnum
rather than offset, bitpos and byte_offset. Split the plain move
cases into two, one for memory accesses and one for register accesses.
Allow simplify_gen_subreg to fail rather than calling validate_subreg.
Move the handling of multiword OP0s after the code that coerces VALUE
to an integer mode. Use simplify_gen_subreg for this case and assert
that it succeeds. If the field still spans several words, pass it
directly to store_split_bit_field. Assume after that point that
both sources and register targets fit within a word. Replace
x-prefixed variables with non-prefixed forms. Compute the bitpos
for insv register operands directly in the chosen unit size, rather
than going through an intermediate BITS_PER_WORD unit size.
Update the call to store_fixed_bit_field.
(store_fixed_bit_field): Replace the bitpos and offset parameters
with a single bitnum parameter, of the same form as store_bit_field.
Assume that OP0 contains the full field. Simplify the memory offset
calculation. Assert that the processed OP0 has an integral mode.
(store_split_bit_field): Update the call to store_fixed_bit_field.
Ian Bolton [Tue, 23 Oct 2012 17:35:16 +0000 (17:35 +0000)]
AArch64 [1/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
James Greenhalgh <james.greenhalgh@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen.thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
Ian Bolton [Tue, 23 Oct 2012 17:27:13 +0000 (17:27 +0000)]
AArch64 [8/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen.thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* config.host (aarch64*-*-elf, aarch64*-*-linux*): New.
* config/aarch64/crti.S: New file.
* config/aarch64/crtn.S: New file.
* config/aarch64/linux-unwind.h: New file.
* config/aarch64/sfp-machine.h: New file.
* config/aarch64/sync-cache.c: New file.
* config/aarch64/t-aarch64: New file.
* config/aarch64/t-softfp: New file.
Co-Authored-By: Jim MacArthur <jim.macarthur@arm.com> Co-Authored-By: Marcus Shawcroft <marcus.shawcroft@arm.com> Co-Authored-By: Nigel Stephens <nigel.stephens@arm.com> Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Co-Authored-By: Richard Earnshaw <rearnsha@arm.com> Co-Authored-By: Sofiane Naci <sofiane.naci@arm.com> Co-Authored-By: Stephen Thomas <stephen.thomas@arm.com> Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com> Co-Authored-By: Yufeng Zhang <yufeng.zhang@arm.com>
From-SVN: r192729
Ian Bolton [Tue, 23 Oct 2012 17:20:56 +0000 (17:20 +0000)]
AArch64 [4/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen.thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
Ian Bolton [Tue, 23 Oct 2012 17:13:27 +0000 (17:13 +0000)]
AArch64 [5/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen.thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* gcc.target/aarch64/aapcs/aapcs64.exp: New file.
* gcc.target/aarch64/aapcs/abitest-2.h: New file.
* gcc.target/aarch64/aapcs/abitest-common.h: New file.
* gcc.target/aarch64/aapcs/abitest.S: New file.
* gcc.target/aarch64/aapcs/abitest.h: New file.
* gcc.target/aarch64/aapcs/func-ret-1.c: New file.
* gcc.target/aarch64/aapcs/func-ret-2.c: New file.
* gcc.target/aarch64/aapcs/func-ret-3.c: New file.
* gcc.target/aarch64/aapcs/func-ret-3.x: New file.
* gcc.target/aarch64/aapcs/func-ret-4.c: New file.
* gcc.target/aarch64/aapcs/func-ret-4.x: New file.
* gcc.target/aarch64/aapcs/ice_1.c: New file.
* gcc.target/aarch64/aapcs/ice_2.c: New file.
* gcc.target/aarch64/aapcs/ice_3.c: New file.
* gcc.target/aarch64/aapcs/ice_4.c: New file.
* gcc.target/aarch64/aapcs/ice_5.c: New file.
* gcc.target/aarch64/aapcs/macro-def.h: New file.
* gcc.target/aarch64/aapcs/test_1.c: New file.
* gcc.target/aarch64/aapcs/test_10.c: New file.
* gcc.target/aarch64/aapcs/test_11.c: New file.
* gcc.target/aarch64/aapcs/test_12.c: New file.
* gcc.target/aarch64/aapcs/test_13.c: New file.
* gcc.target/aarch64/aapcs/test_14.c: New file.
* gcc.target/aarch64/aapcs/test_15.c: New file.
* gcc.target/aarch64/aapcs/test_16.c: New file.
* gcc.target/aarch64/aapcs/test_17.c: New file.
* gcc.target/aarch64/aapcs/test_18.c: New file.
* gcc.target/aarch64/aapcs/test_19.c: New file.
* gcc.target/aarch64/aapcs/test_2.c: New file.
* gcc.target/aarch64/aapcs/test_20.c: New file.
* gcc.target/aarch64/aapcs/test_21.c: New file.
* gcc.target/aarch64/aapcs/test_22.c: New file.
* gcc.target/aarch64/aapcs/test_23.c: New file.
* gcc.target/aarch64/aapcs/test_24.c: New file.
* gcc.target/aarch64/aapcs/test_25.c: New file.
* gcc.target/aarch64/aapcs/test_26.c: New file.
* gcc.target/aarch64/aapcs/test_3.c: New file.
* gcc.target/aarch64/aapcs/test_4.c: New file.
* gcc.target/aarch64/aapcs/test_5.c: New file.
* gcc.target/aarch64/aapcs/test_6.c: New file.
* gcc.target/aarch64/aapcs/test_7.c: New file.
* gcc.target/aarch64/aapcs/test_8.c: New file.
* gcc.target/aarch64/aapcs/test_9.c: New file.
* gcc.target/aarch64/aapcs/test_align-1.c: New file.
* gcc.target/aarch64/aapcs/test_align-2.c: New file.
* gcc.target/aarch64/aapcs/test_align-3.c: New file.
* gcc.target/aarch64/aapcs/test_align-4.c: New file.
* gcc.target/aarch64/aapcs/test_complex.c: New file.
* gcc.target/aarch64/aapcs/test_int128.c: New file.
* gcc.target/aarch64/aapcs/test_quad_double.c: New file.
* gcc.target/aarch64/aapcs/type-def.h: New file.
* gcc.target/aarch64/aapcs/va_arg-1.c: New file.
* gcc.target/aarch64/aapcs/va_arg-10.c: New file.
* gcc.target/aarch64/aapcs/va_arg-11.c: New file.
* gcc.target/aarch64/aapcs/va_arg-12.c: New file.
* gcc.target/aarch64/aapcs/va_arg-2.c: New file.
* gcc.target/aarch64/aapcs/va_arg-3.c: New file.
* gcc.target/aarch64/aapcs/va_arg-4.c: New file.
* gcc.target/aarch64/aapcs/va_arg-5.c: New file.
* gcc.target/aarch64/aapcs/va_arg-6.c: New file.
* gcc.target/aarch64/aapcs/va_arg-7.c: New file.
* gcc.target/aarch64/aapcs/va_arg-8.c: New file.
* gcc.target/aarch64/aapcs/va_arg-9.c: New file.
* gcc.target/aarch64/aapcs/validate_memory.h: New file.
* gcc.target/aarch64/aarch64.exp: New file.
* gcc.target/aarch64/adc-1.c: New file.
* gcc.target/aarch64/adc-2.c: New file.
* gcc.target/aarch64/asm-1.c: New file.
* gcc.target/aarch64/clrsb.c: New file.
* gcc.target/aarch64/clz.c: New file.
* gcc.target/aarch64/ctz.c: New file.
* gcc.target/aarch64/csinc-1.c: New file.
* gcc.target/aarch64/csinv-1.c: New file.
* gcc.target/aarch64/csneg-1.c: New file.
* gcc.target/aarch64/extend.c: New file.
* gcc.target/aarch64/fcvt.x: New file.
* gcc.target/aarch64/fcvt_double_int.c: New file.
* gcc.target/aarch64/fcvt_double_long.c: New file.
* gcc.target/aarch64/fcvt_double_uint.c: New file.
* gcc.target/aarch64/fcvt_double_ulong.c: New file.
* gcc.target/aarch64/fcvt_float_int.c: New file.
* gcc.target/aarch64/fcvt_float_long.c: New file.
* gcc.target/aarch64/fcvt_float_uint.c: New file.
* gcc.target/aarch64/fcvt_float_ulong.c: New file.
* gcc.target/aarch64/ffs.c: New file.
* gcc.target/aarch64/fmadd.c: New file.
* gcc.target/aarch64/fnmadd-fastmath.c: New file.
* gcc.target/aarch64/frint.x: New file.
* gcc.target/aarch64/frint_double.c: New file.
* gcc.target/aarch64/frint_float.c: New file.
* gcc.target/aarch64/index.c: New file.
* gcc.target/aarch64/mneg-1.c: New file.
* gcc.target/aarch64/mneg-2.c: New file.
* gcc.target/aarch64/mneg-3.c: New file.
* gcc.target/aarch64/mnegl-1.c: New file.
* gcc.target/aarch64/mnegl-2.c: New file.
* gcc.target/aarch64/narrow_high-intrinsics.c: New file.
* gcc.target/aarch64/pic-constantpool1.c: New file.
* gcc.target/aarch64/pic-symrefplus.c: New file.
* gcc.target/aarch64/predefine_large.c: New file.
* gcc.target/aarch64/predefine_small.c: New file.
* gcc.target/aarch64/predefine_tiny.c: New file.
* gcc.target/aarch64/reload-valid-spoff.c: New file.
* gcc.target/aarch64/scalar_intrinsics.c: New file.
* gcc.target/aarch64/table-intrinsics.c: New file.
* gcc.target/aarch64/tst-1.c: New file.
* gcc.target/aarch64/vect-abs-compile.c: New file.
* gcc.target/aarch64/vect-abs.c: New file.
* gcc.target/aarch64/vect-abs.x: New file.
* gcc.target/aarch64/vect-compile.c: New file.
* gcc.target/aarch64/vect-faddv-compile.c: New file.
* gcc.target/aarch64/vect-faddv.c: New file.
* gcc.target/aarch64/vect-faddv.x: New file.
* gcc.target/aarch64/vect-fmax-fmin-compile.c: New file.
* gcc.target/aarch64/vect-fmax-fmin.c: New file.
* gcc.target/aarch64/vect-fmax-fmin.x: New file.
* gcc.target/aarch64/vect-fmaxv-fminv-compile.c: New file.
* gcc.target/aarch64/vect-fmaxv-fminv.x: New file.
* gcc.target/aarch64/vect-fp-compile.c: New file.
* gcc.target/aarch64/vect-fp.c: New file.
* gcc.target/aarch64/vect-fp.x: New file.
* gcc.target/aarch64/vect-mull-compile.c: New file.
* gcc.target/aarch64/vect-mull.c: New file.
* gcc.target/aarch64/vect-mull.x: New file.
* gcc.target/aarch64/vect.c: New file.
* gcc.target/aarch64/vect.x: New file.
* gcc.target/aarch64/vector_intrinsics.c: New file.
* gcc.target/aarch64/vfp-1.c: New file.
* gcc.target/aarch64/volatile-bitfields-1.c: New file.
* gcc.target/aarch64/volatile-bitfields-2.c: New file.
* gcc.target/aarch64/volatile-bitfields-3.c: New file.
* g++.dg/abi/aarch64_guard1.C: New file.
Co-Authored-By: Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> Co-Authored-By: Jim MacArthur <jim.macarthur@arm.com> Co-Authored-By: Marcus Shawcroft <marcus.shawcroft@arm.com> Co-Authored-By: Nigel Stephens <nigel.stephens@arm.com> Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Co-Authored-By: Richard Earnshaw <rearnsha@arm.com> Co-Authored-By: Sofiane Naci <sofiane.naci@arm.com> Co-Authored-By: Stephen Thomas <stephen.thomas@arm.com> Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com> Co-Authored-By: Yufeng Zhang <yufeng.zhang@arm.com>
From-SVN: r192725
Ian Bolton [Tue, 23 Oct 2012 17:06:03 +0000 (17:06 +0000)]
AArch64 [2/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
James Greenhalgh <james.greenhalgh@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen,thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
Ian Bolton [Tue, 23 Oct 2012 17:02:30 +0000 (17:02 +0000)]
AArch64 [3/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
James Greenhalgh <james.greenhalgh@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen.thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* common/config/aarch64/aarch64-common.c: New file.
* config/aarch64/aarch64-arches.def: New file.
* config/aarch64/aarch64-builtins.c: New file.
* config/aarch64/aarch64-cores.def: New file.
* config/aarch64/aarch64-elf-raw.h: New file.
* config/aarch64/aarch64-elf.h: New file.
* config/aarch64/aarch64-generic.md: New file.
* config/aarch64/aarch64-linux.h: New file.
* config/aarch64/aarch64-modes.def: New file.
* config/aarch64/aarch64-option-extensions.def: New file.
* config/aarch64/aarch64-opts.h: New file.
* config/aarch64/aarch64-protos.h: New file.
* config/aarch64/aarch64-simd.md: New file.
* config/aarch64/aarch64-tune.md: New file.
* config/aarch64/aarch64.c: New file.
* config/aarch64/aarch64.h: New file.
* config/aarch64/aarch64.md: New file.
* config/aarch64/aarch64.opt: New file.
* config/aarch64/arm_neon.h: New file.
* config/aarch64/constraints.md: New file.
* config/aarch64/gentune.sh: New file.
* config/aarch64/iterators.md: New file.
* config/aarch64/large.md: New file.
* config/aarch64/predicates.md: New file.
* config/aarch64/small.md: New file.
* config/aarch64/sync.md: New file.
* config/aarch64/t-aarch64-linux: New file.
* config/aarch64/t-aarch64: New file.
Co-Authored-By: Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> Co-Authored-By: James Greenhalgh <james.greenhalgh@arm.com> Co-Authored-By: Jim MacArthur <jim.macarthur@arm.com> Co-Authored-By: Marcus Shawcroft <marcus.shawcroft@arm.com> Co-Authored-By: Nigel Stephens <nigel.stephens@arm.com> Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Co-Authored-By: Richard Earnshaw <rearnsha@arm.com> Co-Authored-By: Sofiane Naci <sofiane.naci@arm.com> Co-Authored-By: Stephen Thomas <stephen.thomas@arm.com> Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com> Co-Authored-By: Yufeng Zhang <yufeng.zhang@arm.com>
From-SVN: r192723
Jan Hubicka [Tue, 23 Oct 2012 15:15:58 +0000 (15:15 +0000)]
peel-1.c: New testcase.
* gcc.dg/tree-prof/peel-1.c: New testcase.
* loop-unroll.c (decide_peel_simple): Simple peeling makes sense even
with simple loops; bound number of branches only when FDO is not
available.
(decide_unroll_stupid): Mention that num_loop_branches heuristics
is off.
Jan Hubicka [Tue, 23 Oct 2012 10:00:19 +0000 (12:00 +0200)]
re PR tree-optimization/54937 (Invalid loop bound estimate)
PR middle-end/54937
* tree-ssa-loop-niter.c (record_estimate): Do not try to lower
the bound of non-is_exit statements.
(maybe_lower_iteration_bound): Do it here.
(estimate_numbers_of_iterations_loop): Call it.
* gcc.c-torture/execute/pr54937.c: New testcase.
* gcc.dg/tree-ssa/cunroll-2.c: Update.
Jan Hubicka [Tue, 23 Oct 2012 09:57:36 +0000 (11:57 +0200)]
re PR tree-optimization/54967 (ICE in check_loop_closed_ssa_use, at tree-ssa-loop-manip.c:55)
PR middle-end/54967
* cfgloopmanip.c (fix_bb_placements): Add loop_closed_ssa_invalidated;
track basic blocks that moved out of their loops.
(unloop): Likewise.
(remove_path): Update.
(fix_loop_placements): Update.
* tree-ssa-loop-ivcanon.c (try_unroll_loop_completely): Add
loop_closed_ssa_invalidated parameter; pass it around.
(canonicalize_loop_induction_variables): Update loop closed
SSA form if needed.
(tree_unroll_loops_completely): Likewise; do irred update out of
the outer loop; verify that SSA form is closed.
* cfgloop.h (unrloop): Update.
re PR middle-end/55030 (gcc.c-torture/execute/builtins/memcpy-chk.c execution, -Os (et al))
PR middle-end/55030
Revert:
* stmt.c (expand_nl_goto_receiver): Remove almost-copy of
expand_builtin_setjmp_receiver.
(expand_label): Adjust, call expand_builtin_setjmp_receiver
with NULL for the label parameter.
* builtins.c (expand_builtin_setjmp_receiver): Don't clobber
the frame-pointer. Adjust comments.
[HAVE_builtin_setjmp_receiver]: Emit builtin_setjmp_receiver
only if LABEL is non-NULL.
Bill Schmidt [Mon, 22 Oct 2012 22:09:22 +0000 (22:09 +0000)]
re PR tree-optimization/55008 (Internal compiler error : verify_ssa failed)
gcc:
2012-10-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/55008
* gimple-ssa-strength-reduction.c (find_basis_for_candidate): Don't
allow a candidate to be a basis for itself under another interpretation.
gcc/testsuite:
2012-10-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/55008
* gcc.dg/tree-ssa/pr55008.c: New test.
* dumpfile.c (dump_phase_enabled_p): Renamed dump_enabled_p. Update
all callers.
(dump_enabled_p): A new function to check if any of the dump files
is available.
(dump_kind_p): Remove check for current_function_decl. Add check for
dumpfile and alt_dump_file.
* dumpfile.h: Add declaration of dump_enabled_p.
Uros Bizjak [Mon, 22 Oct 2012 13:59:33 +0000 (15:59 +0200)]
i386.c (memory_address_length): Assert that non-null base or index RTXes are registers.
* config/i386/i386.c (memory_address_length): Assert that non-null
base or index RTXes are registers. Do not check for REG RTXes.
Determine addr32 prefix from original base and index RTXes.
Simplify code.
mmix.md ("nonlocal_goto_receiver"): Refer to the frame-pointer as an operand.
* config/mmix/mmix.md ("nonlocal_goto_receiver"): Refer to the
frame-pointer as an operand.
("*nonlocal_goto_receiver_expanded"): Ditto. Use
mmix_output_register_setting instead of naked output_asm_insn for
the offset from the frame-pointer to the saved rO.
* config/mmix/mmix.c (mmix_output_register_setting): Emit NEGU for
values -255..0.
* config/mmix/predicates.md ("frame_pointer_operand"): New.
* config/mmix/constraints.md ("Yf"): New.
stmt.c (expand_nl_goto_receiver): Remove almost-copy of expand_builtin_setjmp_receiver.
* stmt.c (expand_nl_goto_receiver): Remove almost-copy of
expand_builtin_setjmp_receiver.
(expand_label): Adjust, call expand_builtin_setjmp_receiver
with NULL for the label parameter.
* builtins.c (expand_builtin_setjmp_receiver): Don't clobber
the frame-pointer. Adjust comments.
[HAVE_builtin_setjmp_receiver]: Emit builtin_setjmp_receiver
only if LABEL is non-NULL.
Eric Botcazou [Mon, 22 Oct 2012 08:59:10 +0000 (08:59 +0000)]
decl.c (gnat_to_gnu_entity): Force BLKmode on the type if it is passed by reference.
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Array_Type>: Force
BLKmode on the type if it is passed by reference.
<E_Array_Subtype>: Likewise.
<E_Record_Type>: Guard the call to Is_By_Reference_Type predicate.
<E_Record_Subtype>: Likewise.
Eric Botcazou [Mon, 22 Oct 2012 07:27:21 +0000 (07:27 +0000)]
re PR bootstrap/54820 (ada: cannot find -lstdc++ since 4.8.0 20121002)
PR bootstrap/54820
* Makefile.tpl (STAGE1_FLAGS_TO_PASS): New variable.
(all-[+prefix+][+module+]): Pass stage1_args to sub-makes.
(all-stage[+id+]-[+prefix+][+module+]): Likewise, if prev is false.
(clean-stage[+id+]-[+prefix+][+module+]): Likewise, if prev is false.
(host_modules): Set stage1_args to STAGE1_FLAGS_TO_PASS.
* Makefile.in: Regenerate.
* configure.ac (have_static_libs): New variable and associated check.
(stage1-ldflags): Move to after stage1_libs and set to -static-libstdc++
-static-libgcc if stage1_libs is empty and have_static_libs is yes.
* configure: Regenerate.
ada/
* gcc-interface/Make-lang.in (GCC_LINK): Remove hardcoded options.
Uros Bizjak [Sun, 21 Oct 2012 22:12:46 +0000 (00:12 +0200)]
i386-protos.h (memory_address_length): Add new bool argument.
* config/i386/i386-protos.h (memory_address_length): Add new bool
argument. Update all uses.
* config/i386/i386.c (memory_address_length): If not LEA insn, then
add length of addr32 prefix based on mode of base or index register.
(ix86_attr_length_address_default) <TYPE_LEA>: Do not handle SImode
addresses here. Update call to memory_address_length.
(ix86_print_address_operand): Use SImode_address_operand predicate.
* config/i386/predicates.md (SImode_address_operand): New.
* config/i386/i386.md (lea<mode>): Use SImode_address_operand
to calculate "mode" attribute. Use SImode_address_operand predicate
instead of open-coding accepted RTX codes.
PR fortran/54725
* Make-lang.in (CFLAGS-cpp.o): Use TARGET_SYSTEM_ROOT_DEFINE.
* cpp.o (gfc_cpp_init_options): Use it for
setting gfc_cpp_option.sysroot.
Thomas Koenig [Sun, 21 Oct 2012 10:32:02 +0000 (10:32 +0000)]
re PR fortran/54465 (Implement -Wextra for Fortran)
2012-10-21 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/54465
* lang.opt (Wextra): Add.
* invoke.texi: Document that -Wc-binding-type, -Wconversion
and -Wline-truncation are implied by -Wall. Document that
-Wcompare-reals is implied by -Wextra. Document -Wextra.
* options.c (set_Wextra): New function.
(gfc_handle_option): Handle -Wextra.
2012-10-21 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/54465
* gfortran.dg/wextra_1.f: New test.
crti.S: Mark program and data addresses using PRELD.
* config/mmix/crti.S: Mark program and data addresses using PRELD.
Remove typo'd and unnecessary alignment-LOC for .data. Remove
no-longer-needed LDBU insns.
Eric Botcazou [Sat, 20 Oct 2012 21:00:23 +0000 (21:00 +0000)]
re PR middle-end/54315 (unnecessary copy of return value for union)
PR rtl-optimization/54315
* calls.c (expand_call): Don't deal specifically with BLKmode values
returned in naked registers.
* expr.h (copy_blkmode_from_reg): Adjust prototype.
* expr.c (copy_blkmode_from_reg): Rename first parameter into TARGET and
make it required. Assert that SRCREG hasn't BLKmode. Add a couple of
short-circuits for common cases and be prepared for sub-word registers.
(expand_assignment): Call copy_blkmode_from_reg for BLKmode values
returned in naked registers.
(store_expr): Likewise.
(store_field): Likewise.
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