ebotcazou [Sat, 26 Jan 2019 11:34:39 +0000 (11:34 +0000)]
* gcc-interface/decl.c (annotate_value) <INTEGER_CST>: Use test on
the sign bit instead of on the sign of the value.
<PLUS_EXPR>: Turn addition of negative constant into subtraction.
<MULT_EXPR>: Add test for degenerate case.
<BIT_AND_EXPR>: Simplify.
vmakarov [Fri, 25 Jan 2019 22:13:43 +0000 (22:13 +0000)]
2019-01-25 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/888846
* ira.c (process_set_for_memref_referenced_p): New.
(memref_referenced_p): Add new param. Use
process_set_for_memref_referenced_p. Add new switch cases.
(memref_used_between_p): Pass new arg to memref_referenced_p.
rearnsha [Fri, 25 Jan 2019 17:09:33 +0000 (17:09 +0000)]
This is pretty unlikely in real code, but similar to Arm, the AArch64
ABI has a bug with the handling of 128-bit bit-fields, where if the
bit-field dominates the overall alignment the back-end code may end up
passing the argument correctly. This is a regression that started in
gcc-6 when the ABI support code was updated to support overaligned
types. The fix is very similar in concept to the Arm fix. 128-bit
bit-fields are fortunately extremely rare, so I'd be very surprised if
anyone has been bitten by this.
PR target/88469
gcc/
* config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add new
argument ABI_BREAK. Set to true if the calculated alignment has
changed in gcc-9. Check bit-fields for their base type alignment.
(aarch64_layout_arg): Warn if argument passing has changed in gcc-9.
(aarch64_function_arg_boundary): Likewise.
(aarch64_gimplify_va_arg_expr): Likewise.
gcc/testsuite/
* gcc.target/aarch64/aapcs64/test_align-10.c: New test.
* gcc.target/aarch64/aapcs64/test_align-11.c: New test.
* gcc.target/aarch64/aapcs64/test_align-12.c: New test.
rsandifo [Fri, 25 Jan 2019 16:57:32 +0000 (16:57 +0000)]
Fix output_constructor_bitfield handling of wide bitfields (PR89037)
The testcase was failing because we were trying to access
TREE_INT_CST_ELT (x, 1) of a 128-bit integer that was small enough
to need only a single element.
2019-01-25 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR middle-end/89037
* varasm.c (output_constructor_bitfield): Use wi::extract_uhwi
instead of accessing TREE_INT_CST_ELT directly.
gcc/testsuite/
PR middle-end/89037
* gcc.dg/pr89037.c: New test.
vries [Fri, 25 Jan 2019 14:39:58 +0000 (14:39 +0000)]
[libbacktrace] Fix strrchr segfault
Currently, when running a libbacktrace testcase t with .gnu_debuglink to
t.debug, and t.debug having a .gnu_debugaltlink to t.alt.debug, a segfault
is triggered when calling strrchr with a NULL string from
elf_find_debugfile_by_debuglink. The NULL string originates from the elf_add
called for the .gnu_debugaltlink, which uses NULL as filename argument.
Fix this by using "" as filename argument instead.
2019-01-25 Tom de Vries <tdevries@suse.de>
* elf.c (elf_add): When handling .gnu_debugaltlink, call elf_add with
filename == "".
* Makefile.am (TESTS): Add btest_dwz_gnudebuglink.
* Makefile.in: Regenerate.
vries [Fri, 25 Jan 2019 14:39:47 +0000 (14:39 +0000)]
[libbacktrace] Rename dtest to btest_gnudebuglink
Create a pattern rule for copying an existing test-case, separating out the
debug information into a .debug file, and referencing the .debug file from
the copied test-case using a .gnu_debuglink.
2019-01-25 Tom de Vries <tdevries@suse.de>
* Makefile.am: Rewrite dtest rule into "%_gnudebuglink" pattern rule.
(TESTS): Rename dtest to btest_gnudebuglink.
* Makefile.in: Regenerate.
wilco [Fri, 25 Jan 2019 13:29:06 +0000 (13:29 +0000)]
[PATCH][AArch64] Fix generation of tst (PR87763)
The TST instruction no longer matches in all cases due to changes in
Combine. The fix is simple, we now need to allow a subreg as well when
selecting the cc_mode. This fixes the tst_5.c and tst_6.c failures.
rguenth [Fri, 25 Jan 2019 12:46:24 +0000 (12:46 +0000)]
2019-01-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/89049
* tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
Look at the pattern stmt to determine if the stmt is vectorized.
rsandifo [Fri, 25 Jan 2019 12:26:49 +0000 (12:26 +0000)]
[AArch64][SVE] Handle register-register pred_movs
pred_mov<mode> is defined for predicated loads and stores, where
exactly one of the operands is a register. However, the instruction
condition only checked for "one" rather than "exactly one", and
Prathamesh found a case in which combine could fold a predicated
pattern to an all-register pred_mov<mode>. The constraints would
then force one of the registers to memory.
This patch splits all-register forms into a normal move as soon
as possible, but also adds an all-register alternative in case the
instruction doesn't get split before RA (or in case the RA can use
inheritance to avoid a reload).
The testcase for this will be added to aarch64/sve-acle-branch.
2018-01-25 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*pred_mov<mode>)
(pred_mov<mode>): Handle all-register forms using both a new
alternative and a split.
bergner [Thu, 24 Jan 2019 22:48:06 +0000 (22:48 +0000)]
* config/rs6000/altivec.md (build_vector_mask_for_load): Use MEM_P.
* config/rs6000/constraints.md (Q constraint): Use REG_P.
* config/rs6000/darwin.h (PREFERRED_RELOAD_CLASS): Use SYMBOL_REF_P.
* config/rs6000/freebsd64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Use
SYMBOL_REF_P, CONST_INT_P and CONST_DOUBLE_P.
* config/rs6000/linux64.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
* config/rs6000/predicates.md (altivec_register_operand, vint_operand,
vsx_register_operand, vsx_reg_sfsubreg_ok, vfloat_operand,
vlogical_operand, gpc_reg_operand, int_reg_operand,
int_reg_operand_not_pseudo): Use SUBREG_P and HARD_REGISTER_P.
(ca_operand, base_reg_operand, htm_spr_reg_operand, cc_reg_operand,
cc_reg_not_cr0_operand, input_operand): Use SUBREG_P.
(save_world_operation, restore_world_operation, lmw_operation,
stmw_operation): Use MEM_P and REG_P.
(tie_operand): Use MEM_P.
(vrsave_operation, crsave_operation): Use REG_P.
(mfcr_operation, mtcrf_operation): Use REG_P and CONST_INT_P.
(fpr_reg_operand): Use SUBREG_P and HARD_REGISTER_NUM_P.
(quad_int_reg_operand): Use HARD_REGISTER_NUM_P.
(call_operand): Use HARD_REGISTER_P.
(indexed_or_indirect_operand, altivec_indexed_or_indirect_operand):
Use CONST_INT_P.
(lwa_operand): Use SUBREG_P, REG_P and CONST_INT_P.
* config/rs6000/rs6000-p8swap.c (insn_is_load_p, insn_is_store_p,
quad_aligned_load_p, replace_swapped_aligned_store,
recombine_lvx_pattern, replace_swapped_aligned_load,
recombine_stvx_pattern): Use MEM_P.
(const_load_sequence_p, adjust_vperm, replace_swapped_load_constant):
Use MEM_P and SYMBOL_REF_P.
(rtx_is_swappable_p): Use REG_P and CONST_INT_P.
(insn_is_swappable_p): Use REG_P and MEM_P.
(insn_is_swap_p, (alignment_mask): Use CONST_INT_P.
* config/rs6000/rs6000-string.c (expand_block_clear, expand_block_move):
Use CONST_INT_P.
* config/rs6000/rs6000.c (rs6000_secondary_reload, rs6000_emit_cmove):
Use CONST_DOUBLE_P.
(rs6000_output_move_128bit): Use CONST_DOUBLE_P, CONST_INT_P and
CONST_WIDE_INT_P.
(rs6000_legitimize_address): Use CONST_DOUBLE_P, CONST_INT_P,
CONST_WIDE_INT_P, REG_P and SYMBOL_REF_P.
(rs6000_emit_move): Use CONST_DOUBLE_P, CONST_INT_P, HARD_REGISTER_P,
HARD_REGISTER_NUM_P, MEM_P, REG_P, SUBREG_P, SYMBOL_REF_P and
reg_or_subregno:
(output_toc): Use CONST_DOUBLE_P, CONST_INT_P and SYMBOL_REF_P.
(easy_altivec_constant, rs6000_legitimate_offset_address_p,
rs6000_mode_dependent_address, rs6000_expand_mtfsf_builtin,
rs6000_expand_set_fpscr_rn_builtin, rs6000_expand_set_fpscr_drn_builtin,
rs6000_expand_unop_builtin, INT_P, rs6000_generate_compare,
rs6000_machopic_legitimize_pic_address, rs6000_split_logical_inner,
rs6000_split_logical_di): Use CONST_INT_P.
(rs6000_legitimize_reload_address): Use CONST_INT_P, HARD_REGISTER_P,
REG_P and SYMBOL_REF_P.
(setup_incoming_varargs, rs6000_rtx_costs): Use CONST_INT_P and MEM_P.
(print_operand): Use CONST_INT_P, MEM_P and REG_P.
(virtual_stack_registers_memory_p, rs6000_legitimate_address_p,
mems_ok_for_quad_peep): Use CONST_INT_P and REG_P.
(rs6000_secondary_reload_memory): Use CONST_INT_P and SUBREG_P.
(small_data_operand, print_operand_address): Use CONST_INT_P and
SYMBOL_REF_P.
(split_stack_arg_pointer_used_p): Use HARD_REGISTER_P.
(rs6000_init_hard_regno_mode_ok, direct_move_p):
Use HARD_REGISTER_NUM_P.
(rs6000_secondary_reload_gpr): Use HARD_REGISTER_NUM_P and MEM_P.
(rs6000_secondary_reload_class): Use HARD_REGISTER_NUM_P, REG_P,
SUBREG_P and SYMBOL_REF_P.
(register_to_reg_type, rs6000_secondary_reload_inner): Use SUBREG_P
and HARD_REGISTER_NUM_P.
(rs6000_adjust_vec_address): Use HARD_REGISTER_NUM_P and
reg_or_subregno.
(rs6000_adjust_cost, find_mem_ref): Use MEM_P.
(macho_lo_sum_memory_operand, rs6000_eliminate_indexed_memrefs): Use
MEM_P and REG_P.
(legitimate_indirect_address_p, legitimate_lo_sum_address_p,
registers_ok_for_quad_peep, rs6000_output_function_epilogue,
find_addr_reg): Use REG_P.
(altivec_expand_vec_perm_const): Use REG_P and SUBREG_P.
(rs6000_emit_le_vsx_move): Use SUBREG_P.
(offsettable_ok_by_alignment, constant_pool_expr_p,
legitimate_small_data_p, rs6000_output_dwarf_dtprel,
rs6000_delegitimize_address, rs6000_const_not_ok_for_debug_p,
rs6000_cannot_force_const_mem, rs6000_output_addr_const_extra,
rs6000_assemble_integer, create_TOC_reference,
rs6000_emit_allocate_stack, rs6000_xcoff_encode_section_info,
rs6000_call_aix, rs6000_call_aix): Use SYMBOL_REF_P.
(rs6000_split_vec_extract_var): Use reg_or_subregno.
* config/rs6000/rtems.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Use
CONST_DOUBLE_P, CONST_INT_P and SYMBOL_REF_P.
* config/rs6000/sysv4.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
* config/rs6000/xcoff.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
* config/rs6000/rs6000.h (RS6000_SYMBOL_REF_TLS_P): Use SYMBOL_REF_P.
(REGNO_OK_FOR_INDEX_P, REGNO_OK_FOR_BASE_P): Use HARD_REGISTER_NUM_P.
(INT_REG_OK_FOR_INDEX_P, INT_REG_OK_FOR_BASE_P): Use HARD_REGISTER_P.
(CONSTANT_ADDRESS_P): Use CONST_INT_P and SYMBOL_REF_P.
* config/rs6000/rs6000.md (define_expands strlensi, mod<mode>3
and cbranch<mode>4): Use CONST_INT_P.
(multiple define_splits): Use REG_P and SUBREG_P.
(define_expands call, call_value): Use MEM_P.
(define_expands sibcall, sibcall_value): Use CONST_INT_P and MEM_P.
(define insn *mtcrfsi): Use CONST_INT_P and REG_P.
* config/rs6000/vsx.md (*vsx_le_perm_load_<mode>,
*vsx_le_perm_load_v8hi, *vsx_le_perm_load_v16qi): Use HARD_REGISTER_P
and HARD_REGISTER_NUM_P.
(multiple define_splits): Use HARD_REGISTER_NUM_P.
jason [Thu, 24 Jan 2019 21:23:33 +0000 (21:23 +0000)]
PR c++/89001 - mangling of reference temporaries
It used to be the case that the mangled name of a reference temporary didn't
need to be standardized, because all access would be through the reference.
But now constant expressions can look through references and so different
translation units need to agree on the address of a temporary in the
initializer of a reference with vague linkage.
* cp-tree.h (struct saved_scope): Add ref_temp_count.
(current_ref_temp_count): New macro.
* mangle.c (mangle_ref_init_variable): Use it.
* typeck2.c (store_init_value): Clear it.
* call.c (make_temporary_var_for_ref_to_temp): Copy public and
comdat.
msebor [Thu, 24 Jan 2019 21:06:01 +0000 (21:06 +0000)]
PR c/86125 - missing -Wbuiltin-declaration-mismatch on a mismatched return type
PR middle-end/86308 - ICE in verify_gimple calling index() with an invalid declaration
PR c/86125 - missing -Wbuiltin-declaration-mismatch on a mismatched return type
PR c/88886 - [9 Regression] ice in get_constant, at c-family/c-format.c:292
gcc/c/ChangeLog:
PR c/86125
PR c/88886
PR middle-end/86308
* c-decl.c (match_builtin_function_types): Add arguments.
(diagnose_mismatched_decls): Diagnose mismatched declarations
of built-ins more strictly.
gcc/testsuite/ChangeLog:
PR c/86125
PR c/88886
PR middle-end/86308
* gcc.dg/Wbuiltin-declaration-mismatch-6.c: New test.
* gcc.dg/Wbuiltin-declaration-mismatch-7.c: New test.
* gcc.dg/Wbuiltin-declaration-mismatch-8.c: New test.
* gcc.dg/Wbuiltin-declaration-mismatch-9.c: New test.
* gcc.dg/Wbuiltin-declaration-mismatch-10.c: New test.
* gcc.dg/builtins-69.c: New test.
* gcc.dg/Wint-conversion-2.c: Add expected warning.
* gcc.c-torture/execute/eeprof-1.c: Adjust function signatures.
uros [Thu, 24 Jan 2019 20:48:01 +0000 (20:48 +0000)]
PR target/88948
* rtl.h (prepare_copy_insn): New prototype.
* gcse.c (prepare_copy_insn): New function, split out from
process_insert_insn.
(process_insert_insn): Use prepare_copy_insn.
* store-motion.c (replace_store_insn): Use prepare_copy_insn
instead of gen_move_insn.
testsuite/ChangeLog:
PR target/88948
* gcc.target/i386/pr88948.c: New test.
jakub [Thu, 24 Jan 2019 19:16:21 +0000 (19:16 +0000)]
PR c++/88976
* c-typeck.c (c_finish_omp_cancel): Diagnose more than one if
on #pragma omp cancel with different modifiers.
* semantics.c (finish_omp_cancel): Diagnose more than one if
on #pragma omp cancel with different modifiers. Use
maybe_convert_cond when not in template or build_x_binary_op
otherwise.
* c-c++-common/gomp/cancel-2.c: New test.
* gcc.dg/gomp/cancel-1.c: New test.
* g++.dg/gomp/cancel-1.C: New test.
* g++.dg/gomp/cancel-2.C: New test.
* g++.dg/gomp/cancel-3.C: New test.
rearnsha [Thu, 24 Jan 2019 16:06:34 +0000 (16:06 +0000)]
Mitigation for PR target/88469 on arm-based systems bootstrapping with gcc-6/7/8
This patch, for gcc 8/9 is a mitigation patch for PR target/88469
where gcc-6/7/8 miscompile a structure whose alignment is dominated by
a 64-bit bitfield member. Since the PCS rules for such a type must
ignore any overalignment of the base type we cannot address this by
simply adding a larger alignment to the class. We can, however, force
the alignment of the bit-field itself and GCC will handle that as
desired.
PR target/88469
* profile-count.h (profile_count): On ARM systems using GCC 6/7/8
force the alignment of m_val.
redi [Thu, 24 Jan 2019 15:39:25 +0000 (15:39 +0000)]
PR libstdc++/88840 delay evaluation of constant until type is complete
Clang fails to compile std::vector<Incomplete> because the static member
__use_relocate cannot be evaluated for an incomplete type. Replace with
a static member function that will not be odr-used until needed, by
which point the type must be complete.
PR libstdc++/88840
* include/bits/stl_vector.h (vector::__use_relocate): Replace static
data member with static member function _S_use_relocate().
* include/bits/vector.tcc (vector::reserve, vector::_M_realloc_insert)
(vector::_M_default_append): Use _S_use_relocate() instead of
__use_relocate.
marxin [Thu, 24 Jan 2019 08:27:39 +0000 (08:27 +0000)]
Fix broken filename for .gcda files starting with '..' (PR gcov-profile/88994).
2019-01-24 Martin Liska <mliska@suse.cz>
PR gcov-profile/88994
* gcov-io.c (mangle_path): Do not allocate a bigger buffer,
result will be always smaller or equal to the original.
* gcov.c (mangle_name): Fix else branch where we should
also copy to PTR and shift the pointer.
pault [Thu, 24 Jan 2019 07:21:36 +0000 (07:21 +0000)]
2019-01-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/88929
* trans-array.c (gfc_conv_descriptor_elem_len): New function.
* trans-array.h : Add prototype for above.
* trans-expr.c (gfc_conv_gfc_desc_to_cfi_desc): Take account of
assumed rank arrays being flagged by rank = -1 in expressions.
Intent in arrays need a pointer to a copy of the data to be
assigned to the descriptor passed for conversion. This should
then be freed, together with the CFI descriptor on return from
the C call.
2019-01-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/88929
* gfortran.dg/ISO_Fortran_binding_3.f90 : New test
* gfortran.dg/ISO_Fortran_binding_3.c : Subsidiary source.
pault [Thu, 24 Jan 2019 07:19:49 +0000 (07:19 +0000)]
2019-01-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/88929
* trans-array.c (gfc_conv_descriptor_elem_len): New function.
* trans-array.h : Add prototype for above.
* trans-expr.c (gfc_conv_gfc_desc_to_cfi_desc): Take account of
assumed rank arrays being flagged by rank = -1 in expressions.
Intent in arrays need a pointer to a copy of the data to be
assigned to the descriptor passed for conversion. This should
then be freed, together with the CFI descriptor on return from
the C call.
2019-01-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/88929
* gfortran.dg/ISO_Fortran_binding_3.f90 : New test
* gfortran.dg/ISO_Fortran_binding_3.c : Subsidiary source.
mpolacek [Wed, 23 Jan 2019 17:25:42 +0000 (17:25 +0000)]
PR c++/88757 - qualified name treated wrongly as type.
* parser.c (cp_parser_direct_declarator): don't treat qualified-ids
in parameter-list as types if name lookup for declarator-id didn't
find one or more function templates.
* g++.dg/cpp0x/dependent2.c: new test.
* g++.dg/cpp2a/typename10.c: remove dg-error.
* g++.dg/cpp2a/typename12.c: new test.
* g++.dg/template/static30.c: remove dg-error.
dmalcolm [Wed, 23 Jan 2019 16:36:46 +0000 (16:36 +0000)]
aarch64: fix use-after-free in -march=native (PR driver/89014)
Running:
$ valgrind ./xgcc -B. -c test.c -march=native
on aarch64 shows a use-after-free in host_detect_local_cpu due
to the std::string result of aarch64_get_extension_string_for_isa_flags
only living until immediately after a c_str call.
This leads to corrupt "-march=" values being passed to cc1.
This patch fixes the use-after-free, though it appears to also need
Tamar's patch here:
https://gcc.gnu.org/ml/gcc-patches/2018-12/msg01302.html
in order to generate valid values for cc1. This may have worked by
accident in the past, if the corrupt "-march=" value happened to be
0-terminated in the "right" place; with this patch it now appears
to reliably break without Tamar's patch.
gcc/ChangeLog:
PR driver/89014
* config/aarch64/driver-aarch64.c (host_detect_local_cpu): Fix
use-after-free of the result of
aarch64_get_extension_string_for_isa_flags.
ebotcazou [Wed, 23 Jan 2019 11:07:56 +0000 (11:07 +0000)]
* cgraphunit.c (cgraph_node::expand_thunk): When expanding a GIMPLE
thunk that returns by reference, use the type of the return object
of the thunk instead of that of the alias to build the dereference.
claziss [Wed, 23 Jan 2019 11:04:19 +0000 (11:04 +0000)]
[ARC] atomics: Add operand to DMB instruction
Atomics use DMB instruction to enforce ordering of loads/stores.
Currently gcc generates DMB w/o any arg which is a no-op. Fix that by
generating DMB 3 which enforces R+W ordering. It is stricter than what
acq/rel expect, but there's no other way.
gcc/
2019-xx-xx Vineet Gupta <vgupta@synopsys.com>
* config/arc/atomic.md: Add operand to DMB instruction
vries [Wed, 23 Jan 2019 10:22:43 +0000 (10:22 +0000)]
[libbacktrace] Use size_t for low_offset/high_offset fields of struct unit
2019-01-23 Tom de Vries <tdevries@suse.de>
* dwarf.c (struct unit): Use size_t for low_offset/high_offset fields.
(units_search, find_unit): Use size_t for offset.
(build_address_map): Use size_t for unit_offset.
jakub [Wed, 23 Jan 2019 08:35:38 +0000 (08:35 +0000)]
PR tree-optimization/88964
* gimple-loop-interchange.cc (loop_cand::analyze_induction_var): Use
build_zero_cst instead of build_int_cst. Return false for loop
invariants which honor signed zeros.
vries [Wed, 23 Jan 2019 08:16:56 +0000 (08:16 +0000)]
[nvptx, libgomp] Fix cuMemAlloc with size zero
Consider test-case:
...
int
main (void)
{
#pragma acc parallel async
;
#pragma acc parallel async
;
#pragma acc wait
return 0;
}
...
This fails with:
...
libgomp: cuMemAlloc error: invalid argument
Segmentation fault (core dumped)
...
The cuMemAlloc error is due to the fact that we're try to allocate 0 bytes.
Fix this by preventing calling map_push with size zero argument in nvptx_exec.
This also has the consequence that for the abort-1.c test-case, we end up
calling cuMemFree during map_fini for the struct cuda_map allocated in
map_init, which fails because an abort happened. Fix this by calling
cuMemFree with CUDA_CALL_NOCHECK in cuda_map_destroy.
2019-01-23 Tom de Vries <tdevries@suse.de>
PR target/PR88946
* plugin/plugin-nvptx.c (cuda_map_destroy): Use CUDA_CALL_NOCHECK for
cuMemFree.
(nvptx_exec): Don't call map_push if mapnum == 0.
* testsuite/libgomp.oacc-c-c++-common/pr88946.c: New test.
vries [Wed, 23 Jan 2019 08:16:42 +0000 (08:16 +0000)]
[nvptx, libgomp] Fix assert (!s->map->active) in map_fini
There are currently two situations where this assert triggers:
...
libgomp/plugin/plugin-nvptx.c: map_fini: Assertion `!s->map->active' failed.
...
First, in abort-1.c, a parallel region triggering an abort:
...
int
main (void)
{
#pragma acc parallel
abort ();
return 0;
}
...
The abort is detected in nvptx_exec as the CUDA_ERROR_ILLEGAL_INSTRUCTION
return status of the cuStreamSynchronize call after kernel launch, which is
then handled by calling non-returning function GOMP_PLUGIN_fatal.
Consequently, the map_pop in nvptx_exec that in case of cuStreamSynchronize
success would remove or inactive the element added by the map_push earlier in
nvptx_exec, does not trigger. With the element no longer active, but still
marked active and a member of s->map, we run into the assert during
GOMP_OFFLOAD_fini_device, which is triggered from atexit handler
gomp_target_fini (which is triggered by the GOMP_PLUGIN_fatal mentioned above
calling exit).
Second, in pr88941.c, an async parallel region without wait:
...
int
main (void)
{
#pragma acc parallel async
;
/* no #pragma acc wait */
return 0;
}
...
Because nvptx_exec is handling an async region, it does not call map_pop for
the element added by map_push, but schedules an kernel execution completion
event to call map_pop. Again, we run into the assert during
GOMP_OFFLOAD_fini_device, which is triggered from atexit handler
gomp_target_fini, but the exit in this case is triggered by returning from main.
So either the kernel is still running, or the kernel has completed but the
corresponding event that is supposed to call map_pop is stuck in the event
queue, waiting for an event_gc.
Fix this by removing the assert, and skipping the freeing of device memory if
the map is still marked active (though in the async case, this is more a
workaround than an fix).
vries [Wed, 23 Jan 2019 08:16:11 +0000 (08:16 +0000)]
[nvptx, libgomp] Fix map_push
The map field of a struct ptx_stream is a FIFO. The FIFO is implemented as a
single linked list, with pop-from-the-front semantics.
The function map_pop pops an element, either by:
- deallocating the element, if there is more than one element
- or marking the element inactive, if there's only one element
The responsibility of map_push is to push an element to the back, as well as
selecting the element to push, by:
- allocating an element, or
- reusing the element at the front if inactive and big enough, or
- dropping the element at the front if inactive and not big enough, and
allocating one that's big enough
The current implemention gets at least the first and most basic scenario wrong:
> map = cuda_map_create (size);
We create an element, and assign it to map.
> for (t = s->map; t->next != NULL; t = t->next)
> ;
We determine the last element in the fifo.
> t->next = map;
We append the new element.
> s->map = map;
But here, we throw away the rest of the FIFO, and declare the FIFO to be just
the new element.
This problem causes the test-case asyncwait-1.c to fail intermittently on some
systems. The pr87835.c test-case added here is a a minimized and modified
version of asyncwait-1.c (avoiding the kernel construct) that is more likely to
fail.
Fix this by rewriting map_pop more robustly, by:
- seperating the function in two phases: select element, push element
- when reusing or dropping an element, making sure that the element is cleanly
popped from the queue
- rewriting the push element part in such a way that it can handle all cases
without needing if statements, such that each line is exercised for each of
the three cases.
2019-01-23 Tom de Vries <tdevries@suse.de>
PR target/87835
* plugin/plugin-nvptx.c (map_push): Fix adding of allocated element.
* testsuite/libgomp.oacc-c-c++-common/pr87835.c: New test.
msebor [Wed, 23 Jan 2019 00:23:21 +0000 (00:23 +0000)]
gcc/testsuite/ChangeLog:
* c-c++-common/Warray-bounds-2.c: Include headers only if they exist.
* c-c++-common/Warray-bounds-3.c: Make xfails conditional on target
non_strict_align.
* c-c++-common/Wrestrict-2.c: Include headers only if they exist.
* c-c++-common/Wrestrict.c: Make xfails conditional on target
non_strict_align.
jakub [Tue, 22 Jan 2019 22:30:44 +0000 (22:30 +0000)]
PR target/88965
* config/rs6000/rs6000.c: Include tree-vrp.h and tree-ssanames.h.
(rs6000_gimple_fold_builtin): If MEM_REF address doesn't satisfy
is_gimple_mem_ref_addr predicate, force it into a SSA_NAME first.
rearnsha [Tue, 22 Jan 2019 17:56:02 +0000 (17:56 +0000)]
[arm] Further fixes for PR88469
A bitfield that is exactly the same size as an integral type and
naturally aligned will have DECL_BIT_FIELD cleared. So we need to
check DECL_BIT_FIELD_TYPE to be sure whether or not the underlying
type was declared with a bitfield declaration.
I've also added a test for bitfields that are based on overaligned types.
wilco [Tue, 22 Jan 2019 17:49:46 +0000 (17:49 +0000)]
Fix vect-nop-move.c test
Fix a failing test - changes in Combine mean the test now fails
eventhough the generated code is the same. Given there are several
AArch64-specific tests for vec-select, remove the scanning of Combine
output. Committed as trivial fix.
testsuite/
PR rtl-optimization/87763
* gcc.dg/vect/vect-nop-move.c: Fix testcase on AArch64.
Since "mask" is used for both ix86_isa_flags and ix86_isa_flags2, buitins
with both flags can't be handled easily. This patch adds mask2 to
builtin_description to handle it properly.
2019-01-22 Hongtao Liu <hongtao.liu@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
PR target/88909
* config/i386/i386-builtin.def: Add mask2 to all builtin
initializations. Merge ARGS2 and SPECIAL_ARGS2 into ARGS and
SPECIAL_ARGS.
* config/i386/i386.c (BDESC): Add mask2 to the definition.
(BDESC_FIRST): Likewise.
(define_builtin): Add an argument for mask2. Updated to handle
both ix86_isa_flags and ix86_isa_flags2.
(define_builtin_const): Likewise.
(define_builtin_pure): Likewise.
(define_builtin2): Deleted.
(define_builtin_const2): Likewise.
(builtin_description): Add a member, mask2.
(bdesc_*): Add mask2 to builtin initializations.
(ix86_init_mmx_sse_builtins): Update calls to def_builtin,
def_builtin_const and def_builtin_pure. Remove SPECIAL_ARGS2
support.
(ix86_get_builtin_func_type): Remove SPECIAL_ARGS2 support.
ian [Tue, 22 Jan 2019 15:43:40 +0000 (15:43 +0000)]
golang.org/x/tools/go/analysis: pass "gccgo" to types.SizesFor
For the gofrontend copy, change calls to types.SizesFor to pass
"gccgo" rather than "gc". Leave the asmdecl pass unchanged since that
pass is gc-specific anyhow.
This has been fixed in a better way in the external repo by
https://golang.org/cl/158317 and friends, but that is not in 1.12, so
use this approach for now.
rearnsha [Tue, 22 Jan 2019 14:03:22 +0000 (14:03 +0000)]
[arm] PR target/88469 fix incorrect argument passing with 64-bit bitfields
Unfortunately another PCS bug has come to light with the layout of
structs whose alignment is dominated by a 64-bit bitfield element.
Such fields in the type list appear to have alignment 1, but in
reality, for the purposes of alignment of the underlying structure,
the alignment is derived from the underlying bitfield's type. We've
been getting this wrong since support for over-aligned record types
was added several releases back. Worse still, the existing code may
generate unaligned memory accesses that may fault on some versions of
the architecture.
I've taken the opportunity to add a few more tests that check the
passing arguments with overalignment in the PCS. Looking through the
existing tests it looked like they were really only checking
self-consistency and not the precise location of the arguments.
PR target/88469
gcc:
* config/arm/arm.c (arm_needs_doubleword_align): Return 2 if a record's
alignment is dominated by a bitfield with 64-bit aligned base type.
(arm_function_arg): Emit a warning if the alignment has changed since
earlier GCC releases.
(arm_function_arg_boundary): Likewise.
(arm_setup_incoming_varargs): Likewise.
gcc/testsuite:
* gcc.target/arm/aapcs/bitfield1.c: New test.
* gcc.target/arm/aapcs/overalign_rec1.c: New test.
* gcc.target/arm/aapcs/overalign_rec2.c: New test.
* gcc.target/arm/aapcs/overalign_rec3.c: New test.
jakub [Tue, 22 Jan 2019 09:58:23 +0000 (09:58 +0000)]
PR tree-optimization/88044
* tree-ssa-loop-niter.c (number_of_iterations_cond): If condition
is false in the first iteration, but !every_iteration, return false
instead of true with niter->niter zero.
rguenth [Tue, 22 Jan 2019 08:30:51 +0000 (08:30 +0000)]
2019-01-22 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vect_analyze_loop_operations): Use
auto_vec for cost vector to fix memleak.
(vectorize_fold_left_reduction): Properly gather SLP defs.
(vectorizable_comparison): Do not swap operands to properly
gather SLP defs.
amodra [Tue, 22 Jan 2019 02:29:47 +0000 (02:29 +0000)]
[RS6000] PR88614, output_operand: invalid %z value
The direct cause of this PR is the fact that tls_gdld_nomark didn't
handle indirect calls. Also, most indirect calls were being optimised
back to direct calls anyway, due to tls_gdld_nomark not checking any
of the parallel elements except the first (plus the extra element that
distinguishes this call from normal calls). There were other unwanted
substitutions too.
So this patch attacks the problem of handling special calls in a
different way. Rather than adding another element to the call insn
parallel to distinguish -mno-tls-markers __tls_get_addr calls from any
other calls, we now inspect the second CALL arg. Each
call_value_nonlocal and call_value_indirect insn now checks for the
tlsgd/ld unspecs when !TARGET_TLS_MARKERS and emits the arg setup
insns. I disallow the local call patterns since we'll only see local
calls to __tls_get_addr in testcases, and it doesn't seem a good idea
to complicate the patterns just for a minor optimisation. Sibling
call insns aren't used for libcalls, so none of these insns need to
change.
The patch also fixes a minor problem with -mno-tls-markers
__tls_get_addr calls causing a "li 3,0" instruction to be emitted
prior to the arg setup instructions, due to using a libcall with one
arg. That isn't correct when the call insn itself sets up its arg.
Also, I've tidied the V4 secure-plt calls, generating them in
rs6000_call_sysv rather than by splitting in rs6000.md. The
CALL_INSN_FUNCTION_USAGE added in edit_tls_call_insn is no longer
needed (since git commit 0a4b5c66df9).
On the subject of unwanted substitutions, I also saw a
_GLOBAL_OFFSET_TABLE_ symbol_ref being substituted for the GOT reg,
resulting in code like "addi 3,_GLOBAL_OFFSET_TABLE_,tls_ld@got@tlsld".
Fixed by the unspec_tls change.
PR target/88614
* config/rs6000/predicates.md (unspec_tls): Ensure GOT reg
stays a reg. Allow a const_int.
* config/rs6000/rs6000-protos.h (rs6000_output_tlsargs): Declare.
* config/rs6000/rs6000.h (IS_V4_FP_ARGS): Define.
(IS_NOMARK_TLSGETADDR): Define.
* config/rs6000/rs6000.c (edit_tls_call_insn): Delete.
(rs6000_output_tlsargs): New function.
(rs6000_legitimize_tls_address): Don't say a !TARGET_TLS_MARKERS
__tls_get_addr call takes an arg.
(rs6000_call_sysv): Generate sysv4 secure plt call pattern here..
* config/rs6000/rs6000.md (call_nonlocal_sysv): ..rather than here,
delete split..
(call_value_nonlocal_sysv): ..or here, delete split.
(tls_gdld_nomark): Delete.
(call_value_indirect_nonlocal_sysv): Use unspec_tls as operand2
predicate. Call rs6000_output_tlsargs. Adjust length to suit.
(call_value_nonlocal_sysv): Likewise.
(call_value_nonlocal_sysv_secure): Likewise.
(call_value_nonlocal_aix): Likewise.
(call_value_indirect_aix): Likewise.
(call_value_indirect_elfv2): Likewise.
(call_value_local32, call_value_local64): Disable for no-mark tls.
(call_value_local_aix): Likewise.
ian [Mon, 21 Jan 2019 22:58:04 +0000 (22:58 +0000)]
compiler: stop iterator on error
If there is an error reading or parsing an archive header, the
Archive_iterator code would return a dummy header but would not mark
itself as done. The effect is that an invalid archive leads to an
endless loop reading and re-reading the same archive header. Avoid
that by setting the offset to the end of the file, which will cause
the iterator to == archive_end.
No test since it doesn't seem worth constructing an invalid archive.
projects / thirdparty / gcc.git / log
