Luis Machado [Wed, 4 Nov 2020 19:13:05 +0000 (16:13 -0300)]
Support casting capabilities/capability pointers to other types
When casting capabilities and capability pointers to other types, we truncate
the value to the appropriate size, given some capabilities are greater than
8 bytes in size.
gdb/ChangeLog:
2020-11-11 Luis Machado <luis.machado@arm.com>
* valops.c (value_cast): Handle casting from capabilities and
capability pointers.
Luis Machado [Wed, 28 Oct 2020 18:56:36 +0000 (15:56 -0300)]
Invert CSP/PCC and simplify access to C register numbers
This change makes the code more straightforward, since we can expect the order
of the X registers to match that of the C registers. That way we don't have to
deal with ordering issues.
It also simplifies the access to the dynamic C register numbers through the
gdbarch tdep data structure.
gdb/ChangeLog:
2020-11-11 Luis Machado <luis.machado@arm.com>
* aarch64-linux-nat.c (fetch_cregs_from_thread): Invert pcc/csp
order.
* aarch64-linux-tdep.c (aarch64_linux_sigframe_init): Likewise.
* aarch64-tdep.c (aarch64_c_register_names): Likewise.
(aarch64_analyze_prologue): Remove code to handle csp/pcc ordering
issues.
(aarch64_prologue_prev_register): Use new tdep fields.
(aarch64_dwarf2_prev_register): Use new tdep fields and handle lr/clr.
(aarch64_dwarf2_frame_init_reg): Use new tdep fields.
(aarch64_gdbarch_init): Initialize the new tdep fields.
* aarch64-tdep.h (gdbarch_tdep) <cap_reg_clr, cap_reg_csp>
<cap_reg_pcc, cap_reg_rcsp>: New fields
* features/aarch64-capability.c: Regenerate.
* features/aarch64-capability.xml: Invert pcc/csp.
Luis Machado [Mon, 19 Oct 2020 21:46:49 +0000 (18:46 -0300)]
[Morello] Add preliminary core file register set support
Add the register set that is going to be used to read core file data.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-tdep.c (aarch64_linux_cregmap)
(aarch64_linux_cregset): New structs.
(aarch64_linux_iterate_over_regset_sections): Check for capability
registers.
(aarch64_linux_init_abi): Initialize C register set numbers.
Luis Machado [Mon, 19 Oct 2020 20:32:52 +0000 (17:32 -0300)]
[Morello] Fixup manual unwinding without DWARF
Given the use of C registers implies we now have to store 16 bytes worth of
data instead of 8 bytes, we need to adjust the code that handles tracking
register motion and register saving to the stack.
FIXME-Morello: This patch requires changes to opcodes/aarch64-tbl.h so the
a64c instructions carry the proper iclass and opcode information.
Right now, some of the a64c instructions don't carry enough information for
the prologue analyzer to distinguish/group them.
This patch also adds more debugging output.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c (aarch64_analyze_prologue): Handle C registers and
a64c instructions.
(aarch64_scan_prologue): Add debugging output.
* prologue-value.c (pv_area::find_reg): Don't match the register size
exactly, but check if the area size is at least the size of a register.
Luis Machado [Fri, 9 Oct 2020 16:50:17 +0000 (13:50 -0300)]
[Morello] Unwinding: Restore CLR and PCC properly
This patch teaches GDB how to handle restoring CLR and PCC values properly.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c (aarch64_prologue_prev_register): Use LR or CLR
depending on the request.
(aarch64_dwarf_reg_to_regnum): Redirect CLR to LR temporarily.
* aarch64-tdep.h (AARCH64_DWARF_CLR): New constant.
Luis Machado [Wed, 9 Sep 2020 16:09:47 +0000 (13:09 -0300)]
[Morello] Enable DWARF unwinding with C registers
Adjust unwinding functions to cope with the presence of C registers.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c (aarch64_prologue_prev_register): Handle the PCC and
CSP registers. Remove the LSB.
(aarch64_dwarf2_prev_register): Handle CSP, PCC and remove the LSB
from CLR.
(aarch64_dwarf2_frame_init_reg): Handle PCC and CSP.
(aarch64_dwarf_reg_to_regnum): Handle C registers.
Luis Machado [Thu, 1 Oct 2020 18:59:23 +0000 (15:59 -0300)]
[Morello] Record mapping symbols and mark C64 function symbols as special
This patch teaches GDB about AArch64 mapping symbols and special minimal
symbols.
FIXME-Morello: This is currently not actively used, but will be used to detect
capability mode functions later.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c: Include elf-bfd.h.
(MSYMBOL_SET_SPECIAL, MSYMBOL_IS_SPECIAL): New constants.
(aarch64_mapping_symbol): New struct.
(aarch64_mapping_symbol_vec): New typedef.
(aarch64_per_bfd): New struct.
(aarch64_bfd_data_key): New static global.
(aarch64_elf_make_msymbol_special, +aarch64_record_special_symbol): New
function.
(aarch64_gdbarch_init): Register hooks.
Luis Machado [Mon, 28 Sep 2020 19:32:03 +0000 (16:32 -0300)]
[Morello] Disable displaced stepping for Morello
Morello can't support displaced stepping at the moment given it has no API
to write capabilities, which is needed when GDB needs to adjust the X and C
registers during a displaced stepping operation.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-tdep.c (aarch64_linux_init_abi): Only set displaced
stepping hooks for non-Morello targets.
Luis Machado [Thu, 24 Sep 2020 18:09:24 +0000 (15:09 -0300)]
[Morello] Add support for Morello sigreturn/sigcontext frame
This patch teaches GDB how to interpret the Morello sigcontext
structure in a sigreturn frame and allows GDB to read back the
correct values of the registers.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-tdep.c: Include arch/aarch64-insn.h.
(AARCH64_MORELLO_MAGIC, AARCH64_MORELLO_SIGCONTEXT_SIZE)
(AARCH64_MORELLO_SIGCONTEXT_C0_OFFSET): New constants.
(aarch64_linux_sigframe_init): Update to handle Morello
sigreturn/sigcontext frames.
Luis Machado [Thu, 3 Sep 2020 17:20:46 +0000 (14:20 -0300)]
[Morello] Add capability fault codes and report fault information
Report capability faults with additional information, like tag, bounds,
sealed permissions and access faults.
gdb/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-tdep.c: Include value.h.
(aarch64_linux_report_signal_info): New function.
(aarch64_linux_init_abi): Register hook for reporting signal
information.
* arch/aarch64-cap-linux.h (SEGV_CAPTAGERR, SEGV_CAPSEALEDERR)
(SEGV_CAPBOUNDSERR, SEGV_CAPPERMERR, SEGV_CAPSTORETAGERR): New
constants.
Luis Machado [Fri, 17 Jul 2020 20:40:44 +0000 (17:40 -0300)]
[Morello] Add set/show ABI command for AArch64
Add a new command for developers to set and show the AArch64 ABI GDB is
using at the moment.
We define 2 ABI's: AAPCS64 and AAPCS64-cap.
Each of these ABI's should impact the architecture setup in different ways.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c (set_aarch64_cmdlist, show_aarch64_cmdlist,
aarch64_abi_strings, aarch64_current_abi_global)
(aarch64_current_abi_string): New static globals.
(aarch64_update_current_architecture, aarch64_set_abi)
(aarch64_show_abi): New functions.
(aarch64_gdbarch_init): Handle ABI identification.
(_initialize_aarch64_tdep): Add new ABI commands.
* aarch64-tdep.h (aarch64_abi_kind): New enum.
(struct gdbarch_tdep) <abi>: New field.
Luis Machado [Thu, 2 Jul 2020 19:31:11 +0000 (16:31 -0300)]
[General] More capability type handling (merge with others)
Teach more parts of GDB how to handle capabilities properly, add a function
to print capabilities in their natural format and initialize capability types
properly.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* c-typeprint.c (c_type_print_varspec_prefix)
(c_type_print_varspec_suffix): Handle capability type.
* dwarf2/read.c (read_base_type): Call init_capability_type for
capabilities.
* gdbtypes.c (init_capability_type): New function.
(type_align): Handle capability type.
(recursive_dump_type): Likewise.
(arch_capability_type): New function.
(gdbtypes_post_init): Call arch_capability_type for capability
types.
* gdbtypes.h (init_capability_type, arch_capability_type): New
prototypes.
* valprint.c: Include gdbsupport/capability.h.
(generic_value_print_capability): New function.
(generic_value_print): Handle capability types.
Luis Machado [Thu, 5 Mar 2020 17:02:22 +0000 (14:02 -0300)]
[Morello] Add capability register set support
This patch adds capability register set support to both GDB and GDBserver,
allowing the use of ptrace.
gdb/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-nat.c: Include arch/aarch64-cap-linux.h.
(fetch_cregs_from_thread)
(store_cregs_to_thread): New functions.
(aarch64_linux_nat_target::fetch_registers): Modify to check for
capability registers.
* aarch64-linux-tdep.c: Include arch/aarch64-cap-linux.h.
* aarch64-tdep.c (aarch64_cannot_store_register): Check for capability
registers.
(aarch64_gdbarch_init): Also save the last capability register number.
* aarch64-tdep.h (struct gdbarch_tdep) <cap_reg_last>: New field.
* arch/aarch64-cap-linux.h (AARCH64_LINUX_CREGS_SIZE,
AARCH64_MORELLO_REGS_NUM, AARCH64_C_REGS_NUM): New constants.
* arch/aarch64.c: Remove FIXME comment.
* nat/aarch64-linux.h (user_morello_state): New struct.
Luis Machado [Thu, 26 Mar 2020 14:58:01 +0000 (11:58 -0300)]
[Morello] Generate target descriptions based on runtime capability feature checks
This patch adds code to do runtime checks for Morello, so GDB can pick the
correct target description and register set.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-nat.c (aarch64_linux_nat_target::read_description):
Check for HWCAP2_MORELLO.
* aarch64-linux-tdep.c (aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension.
(aarch64_read_description): New parameter capability_p, use it to
generate the proper target description.
(aarch64_gdbarch_init): Update invocation of aarch64_read_description.
* aarch64-tdep.h (aarch64_read_description): New parameter capability_p.
* arch/aarch64.c (aarch64_create_target_description): New parameter
capability_p. Use it.
* arch/aarch64.h (aarch64_create_target_description): New parameter
capability_p.
gdbserver/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* linux-aarch64-ipa.cc (get_ipa_tdesc): Update.
* linux-aarch64-low.cc (aarch64_target::low_arch_setup): Check for
HWCAP2_MORELLO and use it.
* linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension.
(aarch64_linux_read_description): New parameter capability_p. Use it.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): New parameter
capability_p.
Luis Machado [Thu, 12 Mar 2020 19:37:28 +0000 (16:37 -0300)]
[Morello] Add Morello target description XML and registers
This patch adds a Morello register description XML and code to detect and use
said registers.
gdb/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c (aarch64_c_register_names): New static array.
(aarch64_gdbarch_init): Check for capability
XML feature and add registers to the target.
* aarch64-tdep.h (struct gdbarch_tdep) <cap_reg_base>: New field.
<has_capability>: New method.
* arch/aarch64.c: Include features/aarch64-capability.c.
(aarch64_create_target_description): Invoke
create_feature_aarch64_capability.
* features/Makefile (FEATURE_XMLFILES): Add aarch64-capability.xml
* features/aarch64-capability.xml: New file.
* features/aarch64-capability.c: Generate.
Luis Machado [Wed, 1 Apr 2020 19:38:42 +0000 (16:38 -0300)]
[Morello] Initial capability data structure support + Unit testing
This patch adds capability data structures and related functions. These are
Morello-specific, so the encodings only make sense for this particular
Architecture. The capability is restricted to 128 bits, but could be expanded
to hold other variations while keeping the capability class structure.
Unit tests were also included to validate the decoding/encoding functions. The
output is matched against auto-generated values based on a reference
implementation.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* gdb/aarch64-tdep.c: Include gdbsupport/capability.h.
(aarch64_capability_decoding_test): New function.
(_initialize_aarch64_tdep): Register capability tests.
gdbsupport/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* gdbsupport/Makefile.am: Regenerate.
* gdbsupport/Makefile.in: Adjust to include gdbsupport/capability.*.
* gdbsupport/capability.cc: New file.
* gdbsupport/capability.h: New file.
This change adds basic support for TLS descriptors. Relaxation of
TLSDESC_GD to other relocations is limited to TLS_LE, other cases end
up retaining TLSDESC_GD.
There is one key difference from A64 for TLSDESC_GD -> LE transition
and that is in the case of static non-pie binaries. Morello
TLSDESC_GD relocations are relaxed to LE for static non-pie binaries
since it ought to be safe to do so and it aligns with llvm behaviour.
* testsuite/ld-aarch64/morello-tlsdesc.s: New file.
* testsuite/ld-aarch64/morello-tlsdesc.d: New test.
* testsuite/ld-aarch64/morello-tlsdesc-static.d: New test.
* testsuite/ld-aarch64/morello-tlsdesc-staticpie.d: New test.
* testsuite/ld-aarch64/aarch64-elf.exp: Add them.
[Morello] Pad section alignment to account for capability range format
The capability format has limitations on the alignment and length of
capability bounds and are subject to rounding. Add alignment and
padding at the boundaries of such long (typically >16M) sections so
that any capabilities referencing these sections do not end up
overlapping into neighbouring sections.
There are two cases where this is in use. The first and most
important due to the current implementation is the range for PCC,
which needs to span all executable sections and all PLT and GOT
sections. The other case is for linker and ldscript defined symbols
that may be used in dynamic relocations.
* emultempl/aarch64elf.em (elf64_c64_pad_section): New
function.
(gld${EMULATION_NAME}_after_allocation): Resize C64 sections.
* ldlang.c (lang_add_newdot): New function.
* ldlang.h (lang_add_newdot): New function declaration.
* testsuite/ld-aarch64/aarch64-elf.exp: Add new test.
* testsuite/ld-aarch64/morello-sec-round.d: New file.
* testsuite/ld-aarch64/morello-sec-round.ld: New file.
* testsuite/ld-aarch64/morello-sec-round.s: New file.
[Morello] Capability support for exception headers
- Identify and mark C64 frames
- Identify C64 registers including DDC.
- Identify 'purecap' argument to .cfi_startproc for C64 frames
- Emit 'C' in augmentation string for C64 frames
- Recognise the 'C' in the CIE augmentation string when parsing
exception headers
Difference from LLVM: The llvm assembler only uses purecap to add C to
the augmentation string. The GNU assembler on the other hand uses
-march and validates that purecap is passed to .cfi_startproc only for
-morello+c64. This means that for code compiled for A64, if llvm sees
`.cfi_startproc purecap`, it sets 'C' whereas the GNU assembler flags
an error.
* elf-bfd.h (elf_backend_data): New callback
elf_backend_eh_frame_augmentation_char.
* elf-eh-frame.c (_bfd_elf_parse_eh_frame): Use it.
* elfnn-aarch64.c (elf64_aarch64_eh_frame_augmentation_char):
New function.
(elf_backend_eh_frame_augmentation_char): New macro.
* elfxx-target.h [!elf_backend_eh_frame_augmentation_char]:
Set elf_backend_eh_frame_augmentation_char to NULL.
(elfNN_bed): Initialise
elf_backend_eh_frame_augmentation_char.
* config/tc-aarch64.c (REG_DW_CSP, REG_DW_CLR): New macros.
(s_aarch64_cfi_b_key_frame): Adjust for new entry_extras
struct.
(tc_aarch64_frame_initial_instructions): Adjust for C64.
(tc_aarch64_fde_entry_init_extra,
tc_aarch64_cfi_startproc_exp): New functions.
(tc_aarch64_regname_to_dw2regnum): Support capability
registers.
* config/tc-aarch64.h (fde_entry): Forward declaration.
(eh_entry_extras): New struct.
(tc_fde_entry_extras, tc_cie_entry_extras): Use it.
(tc_fde_entry_init_extra): Set to
tc_aarch64_fde_entry_init_extra.
(tc_output_cie_extra): Emit 'C' for C64.
(tc_cie_fde_equivalent_extra): Adjust for C64.
(tc_cie_entry_init_extra): Likewise.
(tc_cfi_startproc_exp): New macro.
(tc_aarch64_cfi_startproc_exp,
tc_aarch64_fde_entry_init_extra): New function declarations.
* dw2gencfi.c (tc_cfi_startproc_exp): New macro.
(dot_cfi_startproc): Use it.
* testsuite/gas/aarch64/morello-eh.d: New test.
* testsuite/gas/aarch64/morello-eh.s: New test.
[Morello] Add interworking and range extension veneers
Add veneers to branch from A64 to C64 and vice versa and for range
extension from C64 to C64. The veneers are named as
__foo_a64c64_veneer, __foo_c64a64_veneer or simply __foo_veneer
(where foo is the target function) based on whether the branch is from
A64 to C64, the other way around or for extended range.
A64 to C64 needs an additional BX since the ADRP in the veneer does
not generate a valid capability without the switch using BX. As a
result, the addendum LSB is no longer important for A64 -> C64 switch,
but we keep it anyway so that we can use the same veneer for long
range C64 to C64 branches.
* elfnn-aarch64.c (STUB_ENTRY_NAME): Add format specifier for
veneer type.
(C64_MAX_ADRP_IMM, C64_MIN_ADRP_IMM): New macros.
(aarch64_branch_reloc_p, c64_valid_for_adrp_p,
aarch64_interwork_stub): New functions.
(aarch64_c64_branch_stub, c64_aarch64_branch_stub): New stubs.
(elf_aarch64_stub_type): New members.
(aarch64_type_of_stub): Support C64 stubs.
(aarch64_lookup_stub_type_suffix): New function.
(elfNN_aarch64_stub_name): Use it.
(elfNN_aarch64_get_stub_entry): Add stub_type argument.
Adjust callers. Support C64 stubs.
(aarch64_build_one_stub): Likewise.
(aarch64_size_one_stub): Likewise.
(elfNN_aarch64_size_stubs): Likewise.
(elfNN_aarch64_build_stubs): Save and return error if stub
building failed.
(elfNN_aarch64_final_link_relocate): Emit stubs based on
whether source and target of a branch are different.
(aarch64_map_one_stub): Emit mapping symbol for C64 stubs.
* testsuite/ld-aarch64/aarch64-elf.exp: Add test.
* testsuite/ld-aarch64/morello-stubs-static.d: New file.
* testsuite/ld-aarch64/morello-stubs.d: New file.
* testsuite/ld-aarch64/morello-stubs.ld: New file.
* testsuite/ld-aarch64/morello-stubs.s: New file.
The jump targets have limited range (i.e. limited by ADRP range) and
hence cannot be used for very long jumps. The linker will throw an
error for such out of range jumps.
- The linker selects morello PLT stubs when it finds at least one
static relocation that needs a capability GOT slot.
- It is assumed that C64 is not compatible with BTI/PAC, so the latter
gets overridden. To allow this, the call to setup_plt_values is
delayed to take into account htab->c64_plt.
- If the caller is A64, the assembler emits R_AARCH64_JUMP_SLOT,
otherwise it emits R_MORELLO_JUMP_SLOT.
- The PLT stub is A64-compatible, in that it should do the right thing
when the execution state is A64.
- If the slots are 16-bytes (this happens when there is at least one
Morello relocation on the GOT), the references in .plt.got and in
.got are always capabilities; the dynamic linker will take care of
that. For PLT, the default trampoline is a capability. This is
true for A64 as well as C64.
- At present it is assumed that there is no interworking between A64
and C64 functions.
* elfnn-aarch64.c (elfNN_c64_small_plt0_entry,
elfNN_c64_small_plt_entry): New variables.
(elfNN_aarch64_howto_table): Add relocations.
(setup_plt_values): Choose C64 PLT when appropriate.
(bfd_elfNN_aarch64_set_options): Defer setup_plt_values
call...
(elfNN_aarch64_link_setup_gnu_properties) ... from here as
well...
(elfNN_aarch64_size_dynamic_sections): ... to here.
(elfNN_aarch64_final_link_relocate,
elfNN_aarch64_check_relocs, elfNN_aarch64_reloc_type_class):
Support new relocations.
(map_symbol_type): New member AARCH64_MAP_C64.
(elfNN_aarch64_output_arch_local_syms): Use it.
(aarch64_update_c64_plt_entry): New function.
(elfNN_aarch64_create_small_pltn_entry): Use it.
(elfNN_aarch64_init_small_plt0_entry): Emit C64 PLT when
appropriate.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add new relocations.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* reloc.c: New relocations BFD_RELOC_MORELLO_TSTBR14,
BFD_RELOC_MORELLO_BRANCH19, BFD_RELOC_MORELLO_JUMP26,
BFD_RELOC_MORELLO_CALL26, BFD_RELOC_MORELLO_JUMP_SLOT and
BFD_RELOC_MORELLO_IRELATIVE.
* bfd-in2.h: Regenerate.
* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/c64-ifunc-2-local.d: New file.
* testsuite/ld-aarch64/c64-ifunc-2.d: New file.
* testsuite/ld-aarch64/c64-ifunc-3a.d: New file.
* testsuite/ld-aarch64/c64-ifunc-3b.d: New file.
* testsuite/ld-aarch64/c64-ifunc-4.d: New file.
* testsuite/ld-aarch64/c64-ifunc-4a.d: New file.
* testsuite/ld-aarch64/ifunc-2-local.s: Support capabilities.
* testsuite/ld-aarch64/ifunc-2.s: Likewise.
[Morello] Add symbol markers for reloc section for static binaries
Add symbols __cap_dynrelocs_start and __cap_dynrelocs_end to mark the
start and end of the .rela.dyn section when building a static
executable without PIE. This allows the runtime startup to traverse
the section and initialise capabilities without having to read the ELF
headers.
All relocations must be of type R_C64_RELATIVE and have the following
properties:
- Frag contains the base of the capability to be initialised
- Frag + 8 has the size and permissions encoded into 56 and 8 bits
respectively
- Addend is the offset from the capability base
- Implement R_MORELLO_LD128_GOT_LO12_NC and emit the correct
relocation based on the target register size.
- Add R_MORELLO_GLOB_DAT and R_MORELLO_RELATIVE dynamic relocations for GOT
entries
- Add support for capabilities in GOT
GOT slots for capabilities need to be 16 byte to accommodate
capabilities. For this purpose, we delay initialising size and
alignment of the GOT sections until we have walked all relocs in
check_relocs. If we encounter capability relocations during the walk,
set the GOT entry size and alignment to account for capabilities or
leave it pointer sized otherwise.
* elfnn-aarch64.c (GOT_ENTRY_SIZE): Adjust for C64
relocations. Adjust callers.
(GOT_RESERVED_HEADER_SLOTS, GOT_CAP): New macros.
(elfNN_aarch64_howto_table): Add R_MORELLO_LD128_GOT_LO12_NC
and R_MORELLO_GLOB_DAT.
(elf_aarch64_link_hash_table): New member c64_rel.
(bfd_elfNN_aarch64_set_options): Initialise it.
(cap_meta, c64_get_capsize): New functions.
(aarch64_reloc_got_type): Use GOT_CAP.
(elfNN_aarch64_final_link_relocate): Add
R_MORELLO_LD128_GOT_LO12_NC and R_MORELLO_GLOB_DAT.
(aarch64_elf_create_got_section): Move section initialisation
into a...
(aarch64_elf_init_got_section): ... New function.
(elfNN_aarch64_size_dynamic_sections): Call it.
(elfNN_aarch64_check_relocs): Add R_MORELLO_LD128_GOT_LO12_NC
and R_MORELLO_GLOB_DAT.
(elfNN_aarch64_finish_dynamic_symbol): Emit C64 relocations
when appropriate.
(elfNN_aarch64_got_elt_size): New function.
(elfNN_aarch64_got_header_size): Return GOT entry size based
on c64_rel.
(elf_backend_got_elt_size): New macro.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add
BFD_RELOC_MORELLO_LD128_GOT_LO12_NC.
* libbfd.h (bfd_reloc_code_real_names): Add
BFD_RELOC_MORELLO_GLOB_DAT and
BFD_RELOC_MORELLO_LD128_GOT_LO12_NC.
* reloc.c: Likewise.
* bfd-in2.h: Regenerate.
* testsuite/ld-aarch64/emit-relocs-morello-1.d: New file.
* testsuite/ld-aarch64/emit-relocs-morello-1.s: New test file.
* testsuite/ld-aarch64/aarch64-elf.exp: Add it to test runner.
Expand GOT slots based on whether we are emitting C64 relocations.
This patch only has infrastructure changes, i.e. it only makes
got_header_size a function and adjusts across architectures.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
Tamar Christina <tamar.christina@arm.com>
* elf-bfd.h (elf_backend_data): Make got_header_size a
function. Add callbacks to all targets that use it.
* elflink.c (_bfd_elf_create_got_section,
bfd_elf_gc_common_finalize_got_offsets,
_bfd_elf_common_section): Adjust got_header_size usage.
* config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type):
Support alternate base loads and stores.
(parse_operands): Support relocations for alternate base
address operands.
* testsuite/gas/aarch64/morello-ldst-reloc.d: New file.
* testsuite/gas/aarch64/morello-ldst-reloc.s: New file.
Introduce three new relocations disguised as two relocations to
support capabilities.
R_MORELLO_CAPINIT is emitted as a static relocation by the assembler
and as a dynamic relocation by the linker; it's a one on one free!
The R_MORELLO_CAPINIT static relocation is emitted by the assembler to
provide capability information to the static linker. The static
linker may do one of two things:
- For local symbols that can be resolved at link time, the static
linker sets up frag and emits a R_MORELLO_RELATIVE dynamic
relocation that the dynamic linker can resolve in a manner similar
to R_AARCH64_RELATIVE. The dynamic linker will have all of the
information it needs (i.e. permissions, size and relative address)
to set up the capability without needing to peek into the symbol
table.
- For dynamic symbols, the static linker emits a R_MORELLO_CAPINIT
with the reference of the dynamic symbol it refers to. The dynamic
linker is then responsible for resolving the symbol at runtime and
setting up the capability based on the properties of the symbol it
is able to deduce.
Linker and Linker script defined symbols
----------------------------------------
For symbols defined by the linker or in linker scripts, capability
size and permissions are based on the section the symbol belongs to.
For linker defined symbols (i.e. _DYNAMIC or _GLOBAL_OFFSET_TABLE_)
this is straightforward since the linker puts them in the correct
section and at the start.
For symbols defined in the linker script, if they are anywhere but the
end of the output script definition, their range becomes the point at
which they are defined, up to the end of the output section. For
symbols defined at the end of the output section, the symbols are
defined with a zero size unless their name is of the form __start_.*
or __.*_start, indicating a start of the section that follows it. In
this case, the symbols are given the range and permission of the
output section following it.
Ideally, the last case (i.e. the heuristic looking for the name)
should be strictly for compatibility and should eventually be fixed in
the linker script to put the symbol into the output section it intends
to track. It may be a useful enhancement to add a warning to that
effect.
* config/tc-aarch64.c (s_aarch64_capinit): New function.
(md_pseudo_table): Use it.
(md_apply_fix): Add BFD_RELOC_MORELLO_CAPINIT.
(aarch64_fix_adjustable): Return FALSE for capabilities.
* testsuite/gas/aarch64/morello-capinit.d: New test file.
* testsuite/gas/aarch64/morello-capinit.s: Likewise.
The opcodes for these instructions overlap with their A64 equivalents;
in fact they're the same with one bit reduced in the immediate. Use
mapping symbols to determine the correct disassembly.
* aarch64-asm.c (aarch64_ins_addr_uimm): Shift only if
F_NOSHIFT is not set.
* aarch64-tbl.h (QL2_B_ADDR, QL2_X_ADDR, QL2_H_ADDR): New
macro.
(aarch64_opcode_table): New instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
The 17-bit signed offset needs to be 16-byte aligned, but the
PCC-relative address resolution rounds down the final address to the
16-byte boundary. Due to this, disassembly of the instruction will
show as if it is loading from the middle of an object.
This branch instructions take an address as their target operand. The
important distinction between the address register usage between these
instructions and other load and store instructions is that these
instructions do not support 64-bit registers as addresses.
* config/aarch64.h (aarch64_operand_class): Add FORM.
(aarch64_opnd): Likewise.
(aarch64_form): New struct.
(aarch64_forms): New array.
(get_form_from_value, get_form_from_str): New functions.
(aarch64_opnd_info): New member FORM.
Disassembly note: RET with capability is always disassembled with the
register name even if it is the default register, i.e. C30. This is
to make it visually simpler to differentiate between the A64 and
Morello RET instructions.
* aarch64-dis.c (aarch64_ext_a64c_immv): New function.
(aarch64_ext_regno): Set PRESENT flag for A64 RET.
* aarch64-dis.h (aarch64_ext_a64c_immv): New function.
* aarch64-opc.c (operand_general_constraint_met_p): Add
A64C_IMMV4. Remove ATTRIBUTE_UNUSED. Reject A64 RET without
operand when in C64.
(aarch64_match_operands_constraint): Remove ATTRIBUTE_UNUSED.
(aarch64_print_operand): Add A64C_IMMV4, Cam_SP and CST_REG.
* aarch64-tbl.h (QL1_A64C_CA, QL3_A64C_CA_CA_CA): New macros.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
[Morello] Add MOV and CPY instructions for capabilities
MOV is an alias of CPY in all cases except when moving CZR into a
capability register (e.g. mov c0, czr), in which case it is treated
as an alias of mov x0, xzr.
[Morello] Identify branch source and target using mapping symbols
Initialise section map data so that it can be used to identify C64
branch targets. This is a reliable way (as long as mapping symbols
are correctly placed!) to identify branch source and target types in
cases where the target type is not STT_FUNC. STT_FUNC targets can
already be identified using the LSB in the symbol table.
Use cases where the branch relocations are used (such as
elfNN_aarch64_size_stubs) have been adjusted to use the symbol cache
instead of reading the symbol table all over again. In addition to
being faster, it will also allow identification of the relocation
targets using the st_target_internal set earlier by check_relocs.
* elf-bfd.h (bfd_elf_section_data): New member
is_target_section_data.
* elfnn-aarch64.c (_aarch64_elf_section_data): New member
sorted.
(elf_aarch64_section_data_get, c64_value_p): New functions.
(elf_aarch64_compare_mapping): Move function up in the file.
(elf_aarch64_obj_tdata): New member secmaps_initialised.
(bfd_elfNN_aarch64_init_maps, bfd_elfNN_aarch64_set_options):
Use it.
(elfNN_aarch64_size_stubs): Use symbol cache.
(elfNN_aarch64_check_relocs): Call
bfd_elfNN_aarch64_init_maps. Mark C64 symbols in relocations
in the symbol cache.
* config/tc-aarch64.c (FIXUP_F_C64): New macro.
(output_inst, parse_operands): Use it.
(aarch64_force_relocation, aarch64_fix_adjustable): Defer
relocation of branches with different source and targets to
the linker.
* config/tc-aarch64.h (aarch64_fix): New member c64.
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Set LSB for C64 symbols.
(elfNN_aarch64_output_map_sym, elfNN_aarch64_output_stub_sym):
Initialise st_target_internal.
(aarch64_elfNN_swap_symbol_in, aarch64_elfNN_swap_symbol_out):
New functions.
(elfNN_aarch64_size_info): Add them as callbacks.
* config/tc-aarch64.c: Include cpu-aarch64.h.
(IS_C64): New macro.
(make_mapping_symbol, aarch64_frob_label): Set LSB of C64
symbol.
(aarch64_adjust_symtab): Mark all C64 functions.
(parse_operands): Set LSB when target of ADR is a function.
(aarch64_fix_adjustable): New function.
* config/tc-aarch64.h (AARCH64_SET_FLAG, AARCH64_RESET_FLAG,
AARCH64_FLAG_C64, AARCH64_IS_C64, AARCH64_SET_C64): New
macros.
(aarch64_fix_adjustable): New function.
(tc_fix_adjustable): Use it.
[Morello] Add mapping symbol to identify C64 code sections
Add a mapping symbol $c at the beginning of every C64 code section to
allow the disassembler to identify C64 code sections. This will allow
the disassembler to print the correct base address registers and also
choose the correct disassembly in cases where the opcodes for A64 and
C64 instructions are aliased.
To aid correct disassembly of instructions, pass CPU variant to
various helpers in libopcodes so that they can use that information to
choose between A64 and C64 disassembly.
The Morello architecture implements support for 129 bit capabilities
to replace traditional pointers to reference memory. A 129 bit
capability has a 64-bit virtual address in its lowest bits and the
next 64 bits have various access control metadata such as bounds
within which the virtual address can be, permissions and other
metadata for protection. The top 129th bit is stored out of band and
it indicates if the capability is valid.
Capability registers extends the 64-bit register file and are
similarly numberd c0 to c30. The stack capability register is csp and
it aliases with sp. One may access the lower 64 bits of the
capability registers by using the 64-bit register names, i.e. x0-x30
and sp. The Arm Architecture Reference Manual Supplement Morello for
A-profile Architecture has more details on the register layout.
To ensure backward compatibiility, processors implementing the Morello
architecture can run in two states, the standard A64 and a new state
called C64. In A64 state, base addresses of memory access
instructions are treated as pointers and traditional aarch64
applications should run out of the box in this state. In C64 state,
base address registers are expected to be valid capabilities.
There are additional load and store instructions that allow using
capabilities as address registers in A64 mode (and 64-bit registers in
C64 mode). These are called alternate base loads and stores.
The following new -march flags are implemented:
- a64c: This is the base feature flag to implement instruction
extensions for Morello that are distinct from its base A64 support.
Address registers are assumed to be 64-bit except for alternate base
loads and stores; they are assumed to be capability registers.
- morello: This enables instructions that are allowed on the Morello
architecture in A64. This includes armv8.2-a, a64c and other
extensions that are considered part of the Morello architecture.
- c64: This enables instructions that are allowed on the Morello
architecture in C64 state. Address registers are assumed to be
capabilities except for alternate base loads and stores; they are
assumed to be 64-bit registers.
To assemble code that is intended to run in A64 state on Morello,
build with -march=morello and for C64 state, build with
-march=morello+c64.
This patch implements bare support for registers and the -march flags.
[AArch64] Prefer error messages from opcodes enabled in CPU_VARIANT
Printing error messages from opcodes that would otherwise not be used
due to not being enabled is pointless when there are other
alternatives. Prefer error messages from enabled opcodes instead.
A more ideal fix would to sort error messages earlier when deciding
which KIND to return. That is, other fatal errors of a less serious
KIND from an enabled opcode should get priority over a more serious
KIND of a disabled opcode.
Tom de Vries [Tue, 20 Oct 2020 08:20:24 +0000 (10:20 +0200)]
[gdb/testsuite] Clean up redundant info in gdb.dwarf2
In gdb.dwarf2/ada-valprint-error.exp we find:
...
untested ${testfile}.exp
...
such that we have:
...
UNTESTED: gdb.dwarf2/ada-valprint-error.exp: ada-valprint-error.exp
...
Fix this and a likewise unsupported message in
gdb.dwarf2/dw2-dir-file-name.exp.
Alan Modra [Tue, 20 Oct 2020 04:29:40 +0000 (14:59 +1030)]
readelf.c display_lto_symtab offset outside bounds of constant string
Using gcc-10 or current mainline gcc, binutils configured with
--disable-nls results in:
readelf.c: In function 'display_lto_symtab':
readelf.c:12283:26: error: offset '17' outside bounds of constant string [-Werror=array-bounds]
12283 | SECTION_NAME (section) + strlen (".gnu.lto_.symtab.")) > 0
| ^
Which is actually a bogus warning in this case because we've already
checked the name string for validity, so SECTION_NAME won't ever be
"<none>", "<no-strings>" or "<corrupt>". This patch fixes the problem
by making SECTION_NAME simply return the string from the string table.
Other places also shouldn't be trying to match any of the error
strings against a section name, so fix them too.
* readelf.c: Delete whitespace at end of line throughout.
(SECTION_NAME, SECTION_NAME_VALID): New.
(SECTION_NAME_PRINT): Rename from SECTION_NAME. Formatting.
(printable_section_name, dump_relocations): Use SECTION_NAME_PRINT.
(process_section_headers, process_section_groups): Likewise.
(shdr_to_ctf_sect): Likewise.
(find_section, find_section_in_set): Use SECTION_NAME_VALID.
(ia64_process_unwind, hppa_process_unwind): Likewise.
(display_debug_section, initialise_dumps_byname): Likewise.
(process_lto_symbol_tables): Likewise. Check trailing period of
lto symbol table names.
(display_lto_symtab): Use sizeof instead of strlen.
Tom Tromey [Mon, 19 Oct 2020 13:45:05 +0000 (07:45 -0600)]
Don't erase TUI source window when switching focus
PR tui/26719 points out that switching the focus can erase the TUI
source window. This is a regression introduced by the patch to switch
the source window to using a pad.
This patch fixes the bug by arranging to call prefresh whenever the
window is refreshed.
2020-10-19 Tom Tromey <tromey@adacore.com>
PR tui/26719
* tui/tui-winsource.h (struct tui_source_window_base)
<refresh_window>: Rename from refresh_pad.
* tui/tui-winsource.c (tui_source_window_base::refresh_window):
Rename from refresh_pad.
(tui_source_window_base::show_source_content)
(tui_source_window_base::do_scroll_horizontal): Update.
gdb/testsuite/ChangeLog
2020-10-19 Tom Tromey <tromey@adacore.com>
(gdb) help info threads
Display currently known threads.
Usage: info threads [OPTION]... [ID]...
Options:
-gid
Show global thread IDs.If ID is given, it is a space-separated list of IDs of threads to display.
Otherwise, all threads are displayed.
(gdb)
I think the "If ID is given ..." info should have come right below
the the usage line. This patch reorganizes the text so that we get
(gdb) help info threads
Display currently known threads.
Usage: info threads [OPTION]... [ID]...
If ID is given, it is a space-separated list of IDs of threads to display.
Otherwise, all threads are displayed.
Options:
-gid
Show global thread IDs.
(gdb)
gdb/ChangeLog:
2020-10-19 Tankut Baris Aktemur <tankut.baris.aktemur@intel.com>
* thread.c (_initialize_thread): Fine-tune the help text of
'info threads'.
Mihails Strasuns [Wed, 14 Oct 2020 08:44:36 +0000 (10:44 +0200)]
gdb: get jiter objfile from a bound minsym
This fixes a regression introduced by the following commit:
fe053b9e853 gdb/jit: pass the jiter objfile as an argument to jit_event_handler
In the refactoring `handle_jit_event` function was changed to pass a matching
objfile pointer to the `jit_event_handler` explicitly, rather using internal
storage:
This was needed to add support for multiple jiters. However it has also
introduced a regression, because `get_frame_function (frame)` here may
return `nullptr`, resulting in a crash.
A more resilient way would be to use an approach mirroring
`jit_breakpoint_re_set` - to find a minimal symbol matching the
breakpoint location and use its object file. We know that this
breakpoint event comes from a breakpoint set by `jit_breakpoint_re_set`,
thus using the reverse approach should be reliable enough.
gdb/Changelog:
2020-10-14 Mihails Strasuns <mihails.strasuns@intel.com>
* breakpoint.c (handle_jit_event): Add an argument, change how
`jit_event_handler` is called.
Nick Clifton [Mon, 19 Oct 2020 14:27:58 +0000 (15:27 +0100)]
Readelf: Add --lto-syms option to display LTO symbol tables.
* readelf.c (do_lto_syms): New local.
(long_option_values): Add OPTION_LTO_SYMS.
(options): Add --lto-syms.
(usage): Mention the new option.
(parse_args): Parse the new option.
(get_lto_kind): New function.
(get_lto_visibility): New function.
(get_lto_sym_type): New function.
(display_lto_symtab): New function - displays the contents of an
LTo symbol table section.
(process_lto_symbol_tables): New functions. Calls
dipslay_lto_symtab on any LTO symbol table section.
(process_object_file): Call process_lto_symbol_tables.
* doc/binutils.texi: Document the new option.
* NEWS: Mention the new feature.
Alan Modra [Sun, 18 Oct 2020 22:19:32 +0000 (08:49 +1030)]
Provide dummy libraries for alpha-vms
alpha-dec-vms always loads a number of libraries, -limagelib,
-lstarlet, and -lsys$public_vectors. When running the ld testsuite
without a full cross-build environment, those libraries are missing
and cause fails. This patch provides dummies, and tidies default.exp
a little.
* testsuite/config/default.exp: Provide dummy libraries for
alpha-dec-vms.
(compiler_supports): New proc. Use it for compiler tests.
* testsuite/lib/ld-lib.exp (default_ld_assemble): Don't die if
subdir not set.
(run_ld_link_tests): Pass LDFLAGS to ld.
* testsuite/ld-checks/checks.exp (section_check): Likewise.
* testsuite/ld-scripts/assert.exp: Likewise.
* testsuite/ld-scripts/extern.exp: Likewise.
* testsuite/ld-scripts/log2.exp: Likewise.
* testsuite/ld-scripts/map-address.exp: Likewise.
* testsuite/ld-scripts/script.exp: Likewise.
* testsuite/ld-scripts/sizeof.exp: Likewise.
Tom Tromey [Sat, 17 Oct 2020 18:34:53 +0000 (12:34 -0600)]
Have partial symbol tables own psymbol vectors
Currently pointers to all partial symbols are stored in two vectors;
and then indices into these vectors are stored in each partial_symtab.
This patch changes this so that each partial symtab instead has
vectors of symbols. add_psymbol_to_list can now be changed into a
method on partial_symtab as well.
My main motivation for doing this is that I am looking into calling
sort_pst_symbols in the background. However, I haven't actually
implemented this yet. (Also this may make it more feasible to also
sort the static psymbols, though I haven't tried that either.)
Also, though, this lets us remove the "current_global_psymbols"
vector, because now the callers can simply refer directly to the
psymtab that they are modifying (formerly this was implicit).
The main drawback of this patch is that it increases the size of
partial symtab.
gdb/ChangeLog
2020-10-17 Tom Tromey <tom@tromey.com>
Tom Tromey [Sat, 17 Oct 2020 17:41:59 +0000 (11:41 -0600)]
Make range types inherit signed-ness from base type
I ran across this comment in valprint.c:
/* FIXME: create_static_range_type does not set the unsigned bit in a
range type (I think it probably should copy it from the target
type), so we won't print values which are too large to
fit in a signed integer correctly. */
It seems to me that a range type ought to inherit its signed-ness from
the underlying type, so this patch implements this change, and removes
the comment. (It was also copied into m2-valprint.c.)
I also remove the comment about handling ranges of enums, because I
think that comment is incorrect.
gdb/ChangeLog
2020-10-17 Tom Tromey <tom@tromey.com>
* valprint.c (generic_value_print): Remove comment.
* m2-valprint.c (m2_value_print_inner): Remove comment.
* gdbtypes.c (create_range_type): Set TYPE_UNSIGNED from base
type.
H.J. Lu [Sat, 17 Oct 2020 11:24:22 +0000 (04:24 -0700)]
gas: Always use as_where for preprocessed assembly codes
Always clear the slot 1 if it was assigned to the input file before the
first .file <NUMBER> directive has been seen. Always use as_where to
generate the correct debug infor for preprocessed assembly codes.
PR gas/25878
PR gas/26740
* dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1
here.
(dwarf2_where): Restore as_where.
(dwarf2_directive_filename): Clear the slot 1 if it was assigned
to the input file.
* testsuite/gas/i386/dwarf5-line-2.d: New file.
* testsuite/gas/i386/dwarf5-line-2.s: Likewise.
* testsuite/gas/i386/dwarf5-line-3.d: Likewise.
* testsuite/gas/i386/dwarf5-line-3.s: Likewise.
* testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and
dwarf5-line-3.
Tom de Vries [Fri, 16 Oct 2020 22:10:31 +0000 (00:10 +0200)]
[gdb/symtab] Handle setting line bp without debug line info
When setting a breakpoint on a line in an executable without debug line info,
we run into an abort.
The problem occurs when calling set_default_source_symtab_and_line, which
calls select_source_symtab (0), which is where we try to find the line number
for main:
...
/* Make the default place to list be the function `main'
if one exists. */
block_symbol bsym = lookup_symbol (main_name (), 0, VAR_DOMAIN, 0);
if (bsym.symbol != nullptr && SYMBOL_CLASS (bsym.symbol) == LOC_BLOCK)
{
symtab_and_line sal = find_function_start_sal (bsym.symbol, true);
loc->set (sal.symtab, std::max (sal.line - (lines_to_list - 1), 1));
return;
}
...
However, due to the missing debug line info, find_function_start_sal returns a
sal with sal.symtab == 0:
...
(gdb) p /x sal
$2 = {pspace = 0x1a4a7f0, symtab = 0x0, symbol = 0x1d9e480, section = 0x1d5b398,
msymbol = 0x0, line = 0x0, pc = 0x4004ab, end = 0x0, explicit_pc = 0x0,
explicit_line = 0x0, is_stmt = 0x0, prob = 0x0, objfile = 0x0}
...
which eventually causes an segfault in create_sals_line_offset because
self->default_symtab->filename is accessed while self->default_symtab == NULL.
Fix this by handling sal.symtab == NULL in select_source_symtab.
Tested on x86_64-linux.
gdb/ChangeLog:
2020-10-17 Tom de Vries <tdevries@suse.de>
PR symtab/26317
* source.c (select_source_symtab): Handling sal.symtab == NULL for
symbol main.
gdb/testsuite/ChangeLog:
2020-10-17 Tom de Vries <tdevries@suse.de>
PR symtab/26317
* gdb.dwarf2/dw2-main-no-line-number.exp: New file.
Tom de Vries [Fri, 16 Oct 2020 22:10:31 +0000 (00:10 +0200)]
[gdb/testsuite] Remove hardcoded filenames in gdb.dwarf2/*.exp
There's a common occurance in dwarf assembly test-cases, where a file test.exp
contains:
...
standard_testfile test.c test-dw.S
...
The "test.c" arg can be abbreviated to ".c".
Make standard_testfile treat args with "-" prefix the same as with "." prefix,
such that we can write:
...
standard_testfile .c -dw.S
...
and apply this in gdb.dwarf2/*.exp.
And though passing `--defsym' does work, if I remove the use of
`--defsym' and just rely on the defaults I get an error:
ld-new: invalid origin for memory region REGION
Interestingly, if I make the above error non-fatal and dump a linker
map file I see that (a) REGION has origin 0x0, and length 0xffff...,
and (b) the symbol from the PROVIDE is provided.
An examination of ldlang.c:lang_process shows us what the issue is,
the origin and length of all memory regions are set as a result of a
single call to lang_do_memory_regions, this call is done after calling
open_input_bfds.
During the open_input_bfds call provide statements can be converted to
provided statements if we know that the assigned symbol is needed, but
for symbols that are only used in the memory regions we are unaware
that we need these symbols.
What I propose in this patch is to make two calls to
lang_do_memory_regions, in the first call we process the expressions
for the origin and length fields of each region, however, errors,
especially undefined symbols, will be ignored. The origin and length
values are not updated. However, by evaluating the expressions any
symbols we need will be added to the symbol table.
Now when we call open_input_bfds, when we process the provide
statements, we will see that the assigned symbol is needed add its new
value to the symbol table.
Finally we reach the original call to lang_do_memory_regions, in
this (now second) call we again process the expressions, and this time
update the origin and length values. Any errors encountered now are
reported to the user.
ld/ChangeLog:
* ldlang.c (lang_process): Add extra call to
lang_do_memory_regions, and pass parameter.
(lang_do_memory_regions): Add parameter, only define origin and
length when requested. Reindent.
* testsuite/ld-scripts/provide-10.d: New file.
* testsuite/ld-scripts/provide-10.map: New file.
* testsuite/ld-scripts/provide-11.d: New file.
* testsuite/ld-scripts/provide-11.map: New file.
* testsuite/ld-scripts/provide-12.d: New file.
* testsuite/ld-scripts/provide-12.map: New file.
* testsuite/ld-scripts/provide-9.d: New file.
* testsuite/ld-scripts/provide-9.map: New file.
* testsuite/ld-scripts/provide-9.t: New file.
projects / thirdparty / binutils-gdb.git / log
